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intel ? lxt971a 3.3v dual-speed fast ethernet phy transceiver datasheet the lxt971a is an ieee compliant fast ethernet phy transceiver that directly supports both 100base-tx and 10base-t appli cations. it provides a media i ndependent interface (mii) for easy attachment to 10/100 medi a access controllers (macs). the lxt971a also provides a low voltage pecl (lvpecl) interface for use with 100base-fx fiber networks. this document also supports the lxt971 device. the lxt971a supports full-duplex operation at 10 mbps and 100 mbps. its operating condition can be set using auto-negotiation, parallel detection, or manual control. the lxt971a is fabricated with an advanced cmos process and requires only a single 3.3v power supply. applications product features combination 10base-t/100base-tx or 100base-fx network interface cards (nics) 10/100 pcmcia cards cable modems and set-top boxes 3.3v operation. low power consumption (300 mw typical). low-power ?sleep? mode. 10base-t and 100base-tx using a single rj-45 connection. supports auto-negotiation and parallel detection. mii interface with extended register capability. robust baseline wander correction performance. 100base-fx fiber-optic capable. standard csma/cd or full-duplex operation. supports jtag boundary scan. configurable via mdio serial port or hardware control pins. integrated, progra mmable led drivers. 64-ball plastic ball grid array (pbga). ? lxt971abc - commercial (0 to 70 c ambient). ? lxt971abe - extended (-40 to 85 c ambient). 64-pin low-profile quad flat package (lqfp). ? lxt971alc - commercial (0 to 70 c ambient). ? lxt971ale - extended (-40 to 85 c ambient). order number: 249414-002 august 2002
2 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or us e of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, lif e saving, life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or ch aracteristics of any features or instructio ns marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt971a may contain design defects or errors known as errata which may cause the product to deviate from published specific ations. current characterized errata are available on request. contact your local intel sales of fice or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document , or other intel lite rature may be obtaine d by calling 1-800-548-4725 or by visiting intel' s website at http://www.intel.com. copyright ? intel corporation, 2002 *third-party brands and names are th e property of their respective owners.
lxt971a 3.3 v dual-speed fast ethernet transceiver datasheet 3 document #: 249414 revision #: 002 rev. date: august 7, 2002 contents 1.0 pin assignments ............................................................................................................. .................12 2.0 signal descriptions ......................................................................................................... .................16 3.0 functional description...................................................................................................... ...............21 3.1 introduction ................................................................................................................ .......21 3.1.1 comprehensive functionality .............................................................................21 3.1.2 osp? architecture ............................................................................................21 3.2 network media / protocol sup port....................................................................................22 3.2.1 10/100 network interface ...................................................................................22 3.2.1.1 twisted-pair interface ..........................................................................22 3.2.1.2 fiber interface.......................................................................................22 3.2.1.3 fault detection and reporting...... ........................................................23 3.2.2 mii data interface...............................................................................................23 3.2.2.1 increased mii drive strength ...............................................................23 3.2.3 configuration management interface .................................................................24 3.2.3.1 mdio management interface ..............................................................24 3.2.3.2 hardware control interface ..................................................................25 3.3 operating requirements....................................................................................................26 3.3.1 power requirements ...........................................................................................26 3.3.2 clock requirements............................................................................................26 3.3.2.1 external crystal/oscillator ...................................................................26 3.3.2.2 mdio clock .........................................................................................26 3.4 initialization.............................................................................................................. .........26 3.4.1 mdio control mode ..........................................................................................26 3.4.2 hardware control mode .....................................................................................27 3.4.3 reduced power modes........................................................................................28 3.4.3.1 hardware power down ........................................................................28 3.4.3.2 software power down..........................................................................29 3.4.3.3 sleep mode ...........................................................................................29 3.4.4 reset....................................................................................................................2 9 3.4.5 hardware configur ation settings........................................................................30 3.5 establishing link........................................................................................................... ....31 3.5.1 auto-negotiation ................................................................................................31 3.5.1.1 base page exchange .............................................................................31 3.5.1.2 next page exchange .............................................................................31 3.5.1.3 controlling auto-negotiation...............................................................31 3.5.2 parallel detection................................................................................................31 3.6 mii operation............................................................................................................... .....32 3.6.1 mii clocks ..........................................................................................................32 3.6.2 transmit enable ..................................................................................................33 3.6.3 receive data valid . .............. .............. .............. .............. .............. .............. ........33 3.6.4 carrier sense .......................................................................................................33 3.6.5 error signals .......................................................................................................33 3.6.6 collision ..............................................................................................................33 3.6.7 loopback.............................................................................................................34 3.6.7.1 operational loopback ..........................................................................35
lxt971a 3.3 v dual-speed fast ethernet transceiver 4 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.6.7.2 test loopback............... .............. .............. .............. ........... ........... ....... 35 3.7 100 mbps operation ......................................................................................................... 3 6 3.7.1 100base-x network operations...................................................................... 36 3.7.2 collision indication ............................................................................................ 38 3.7.3 100base-x protocol sublayer operations ....................................................... 38 3.7.3.1 pcs sublayer ....................................................................................... 38 3.7.3.2 pma sublayer...................................................................................... 41 3.7.3.3 twisted-pair pmd sublayer................................................................ 42 3.7.3.4 fiber pmd sublayer ............................................................................ 43 3.8 10 mbps operation ........................................................................................................... 43 3.8.1 10base-t preamble handling.......................................................................... 43 3.8.2 10base-t carrier sense ................................................................................... 43 3.8.3 10base-t dribble bits ..................................................................................... 43 3.8.4 10base-t link integrity test........................................................................... 44 3.8.4.1 link failure.......................................................................................... 44 3.8.5 10base-t sqe (heartbeat) .............................................................................. 44 3.8.6 10base-t jabber .............................................................................................. 44 3.8.7 10base-t polarity correct ion .......................................................................... 44 3.9 monitoring operations ..................................................................................................... 44 3.9.1 monitoring auto-negotiation ............................................................................ 44 3.9.1.1 monitoring next page exchange......................................................... 45 3.9.2 led functions ................................................................................................... 45 3.9.2.1 led pulse stretching........................................................................... 45 3.10 boundary scan (jtag1149.1) functions ......... .............. .............. .............. .............. ....... 46 3.10.1 boundary scan interface .... .............. .............. .............. ............... .............. ......... 46 3.10.2 state machine..................................................................................................... 46 3.10.3 instruction register ............................................................................................ 46 3.10.4 boundary scan register (b sr)................. .............. .............. ........... ........... ....... 46 4.0 application information..................................................................................................... ............. 48 4.1 magnetics information ..................................................................................................... 48 4.2 typical twisted-pair interface ......................................................................................... 48 4.3 the fiber interface ......................................................................................................... .. 52 5.0 test specifications ......................................................................................................... ................. 56 5.1 electrical parameters ....................................................................................................... .56 5.2 timing diagrams ............................................................................................................. .61 6.0 register definitions ........................................................................................................ ................ 71 7.0 package specifications...................................................................................................... .............. 88 8.0 product ordering information................................................................................................ ......... 90
lxt971a 3.3 v dual-speed fast ethernet transceiver datasheet 5 document #: 249414 revision #: 002 rev. date: august 7, 2002 figures 1 lxt971a block diagram...................................................................................................9 2 64-pin pbga pin assignments.........................................................................................10 3 64-pin lqfp pin assignments..........................................................................................11 4 management interface read frame structure......... .............. .............. ........... ........... ........21 5 management interface write frame structure ............. .............. .............. .............. ...........21 6 interrupt logic............................................................................................................... ....22 7 initialization sequence ......................................................................................................2 4 8 hardware configuration settings .. ....................................................................................26 9 link establishment overview ...........................................................................................28 10 10base-t clocking .........................................................................................................30 11 100base-x clocking ........ .............. .............. .............. .............. .............. .............. ...........30 12 link down clock transition...... .............. ............... .............. .............. ........... ........... ........30 13 loopback paths ............................................................................................................... ..31 14 100base-x frame format.............. .............. .............. .............. .............. .............. ...........32 15 100base-tx data path............. .............. ............... .............. .............. ........... ........... ........33 16 100base-tx reception with no errors.............. .............. .............. .............. ........... ........33 17 100base-tx reception with invalid symbol ....... .............. .............. ........... ........... ........33 18 100base-tx transmission with no errors......... .............. .............. .............. ........... ........34 19 100base-tx transmission with collision......... .............. .............. .............. ........... ........34 20 protocol sublayers........................................................................................................... ..35 21 led pulse stretching ........................................................................................................4 2 22 typical twisted-pair interface - switch............ .............. .............. .............. .............. ........45 23 typical twisted-pair interface - nic............. .............. .............. .............. .............. ...........46 24 typical mii interface ........................................................................................................ 47 25 typical fiber interface ...................................................................................................... 48 26 100base-tx receive timing - 4b mode ............. .............. .............. ........... ........... ........53 27 100base-tx transmit timing - 4b mode............ .............. .............. ........... ........... ........54 28 100base-fx receive timing......... .............. .............. .............. .............. .............. ...........55 29 100base-fx transmit timing .... .............. .............. .............. ............ ........... ........... ........56 30 10base-t receive timing ............. .............. .............. .............. .............. .............. ...........57 31 10base-t transmit timing......... ....................................................................................58 32 10base-t jabber and unjabber ti ming ..........................................................................59 33 10base-t sqe (heartbeat) timing.................................................................................59 34 auto negotiation and fast link pulse timing.. ................................................................60 35 fast link pulse timing .....................................................................................................60 36 mdio input timing ..........................................................................................................61 37 mdio output timing........................................................................................................61 38 power-up timing.............................................................................................................. 62 39 reset pulse width and recovery timing .............. ........................................................62 40 phy identifier bit mapping.... ..........................................................................................68 41 pbga package specification ............................ ................................................................79 42 lxt971a lqfp package specifications..........................................................................80
lxt971a 3.3 v dual-speed fast ethernet transceiver 6 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 tables 1 lqfp numeric pin list .................................................................................................... 12 2 lxt971a mii signal descriptions ................... ............................................................... 14 3 lxt971a network interface signal descriptions .. .............. .............. ........... ........... ....... 15 4 lxt971a miscellaneous signal descriptions ................................................................. 16 5 lxt971a power supply signal descriptions.................................................................. 17 6 lxt971a jtag test signal descriptions ...................................................................... 17 7 lxt971a led signal descriptions ................................................................................ 17 8 hardware configuration settings ..................................................................................... 26 9 carrier sense, loopback, and collision conditions......................................................... 32 10 4b/5b coding ................................................................................................................. .. 36 11 bsr mode of operation ................................................................................................... 43 12 supported jtag instructions ........................................................................................... 43 13 device id register ........................................................................................................... 43 14 magnetics requirements .................................................................................................. 44 15 i/o pin comparison of nic and switch rj-45 se tups..................................................... 44 16 absolute maximum ratings ............................................................................................. 49 17 operating conditions........................................................................................................ 4 9 18 digital i/o characteristics 1 ............................................................................................. 50 19 digital i/o characteristics - mii pins............................................................................... 50 20 i/o characteristics - refclk/xi and xo pins... ............................................................ 50 21 i/o characteristics - led/cfg pins ................................................................................ 50 22 100base-tx transceiver charact eristics....................................................................... 51 23 100base-fx transceiver charact eristics ....................................................................... 51 24 10base-t transceiver characteristics............................................................................ 51 25 10base-t link integrity timing characteristics ........................................................... 52 26 100base-tx receive timing parameters - 4b mode.............. ............... .............. ......... 53 27 100base-tx transmit timing parameters - 4b mode .................................................. 54 28 100base-fx receive timing pa rameters .......... .............. .............. .............. ........... ....... 55 29 100base-fx transmit timing parameters......... ............................................................ 56 30 10base-t receive timing parameters........................................................................... 57 31 10base-t transmit timing parameters ......................................................................... 58 32 10base-t jabber and unjabber timing parameters....................................................... 59 33 10base-t sqe timing parameters ................................................................................ 59 34 auto negotiation and fast link pulse timing parameters .............................................. 60 35 mdio timing parameters ................................................................................................ 61 36 power-up timing parameters .......................................................................................... 62 37 reset pulse width and recovery timing parameters.................................................. 62 38 register set................................................................................................................. ...... 63 39 register bit map............................................................................................................. .. 64 40 control register (address 0) ............................................................................................ 66 41 mii status register #1 (address 1) .................................................................................. 67 42 phy identification register 1 (address 2)....................................................................... 68 43 phy identification register 2 (address 3)....................................................................... 68 44 auto negotiation advertisement register (address 4).................................................... 69 45 auto negotiation link partner base page ab ility register (address 5) ......................... 70 46 auto negotiation expansion (address 6)......................................................................... 71 47 auto negotiation next page transmit regist er (address 7) ........................................... 71 48 auto negotiation link partner next page r eceive register (address 8)............ ............ 72 49 configuration register (address 16, hex 10) .................................................................. 73
lxt971a 3.3 v dual-speed fast ethernet transceiver datasheet 7 document #: 249414 revision #: 002 rev. date: august 7, 2002 50 status register #2 (address 17) ........................................................................................74 51 interrupt enable register (address 18).......... ...................................................................75 52 interrupt status register (address 19, hex 13).................................................................76 53 led configuration register (address 20, hex 14 ) ..........................................................77 54 transmit control register (address 30) ........... ................................................................78
lxt971a 3.3 v dual-speed fast ethernet transceiver 8 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 revision history revision 002 revision date: august 6, 2002 page description globally replaced ?pseudo-pecl? with low-vo ltage pecl?, except when identified with 5 v. 1 front page: changed ?pseudo-ecl (pecl)? to ?low voltage pecl (lvpecl). added ?jtag boundary scan? to product features on front page. 12 modified figure 2 ?lxt971a 64-ball pbga assignments? (replaced test1 and test0 with gnd). 13 modified figure 3 ?lxt971a 64-pin lqfp assignments? (replaced test1 and test0 with gnd). 14 modified table 1 ?lqfp numeric pin list? (replaced test1 and test0 with gnd). 16 added note under section 2.0, ?signal descriptions? : ?intel recommends that all inputs and multi- function pins be tied to the inactive states and all outputs be left floating, if unused.? 17 modified sd/tp description in table 3 ?lxt971a network interface signal descriptions? . added table note 2. 18 modified table 4 ?lxt971a miscellaneous signal descriptions? . 19 modified table 5 ?lxt971a power supply signal descriptions? . 20 added table 8 ?lxt971a pin types and modes? . 22 replaced second paragraph under section 3.2.1.2, ?fiber interface? . 23 added section 3.2.2.1, ?increased mii drive strength? . 23 changed ?far-end fault? title to ?100base-fx far-end fault? . modified first sentence under this heading. 30 modified figure 8 ?hardware configuration settings? . 35 added paragraph after bullets under section 3.6.7.2, ?test loopback? . 43 modified text under section 3.7.3.4, ?fiber pmd sublayer? . 47 modified table 13 ?supported jtag instructions? . 47 modified table 14 ?device id register? . 52 added a new section 4.3, ?the fiber interface? . 53 replaced figure 25 ?typical lxt971a-to-3.3 v fiber transceiver interface circuitry? . 54 added figure 26 ?typical lxt971a-to-5 v fi ber transceiver in terface circuitry? . 55 added figure 27 ?on semiconductor triple pecl-to-lvpecl translator? . 56 modified table 17 ?absolute maximum ratings? . 56 modified table 18 ?operating conditions? : added typ values to vcc current. 57 modified table 20 ?digital i/o characteristics - mii pins? . 58 modified table 22 ?i/o characteri stics - led/cfg pins? . 58 added table 23 ?i/o characte ristics ? sd/tp pin? . 60 added table 28 ?lxt971a thermal characteristics? . 65 modified table 33 ?10base-t receive timing parameters? 72 modified table 42 ?register bit map? . (added table 26 information). 86 added table 57 ?digital config register (address 26)? . 87 modified table 58 ?transmit control register (address 30)? . 90 added section 8.0, ?product ordering information? .
lxt971a 3.3 v dual-speed fast ethernet transceiver datasheet 9 document #: 249414 revision #: 002 rev. date: august 7, 2002 revision 001 revision date: january 2001 page description n/a clock requirements: modified language under clock requirements heading. table 21 i/o characteristics refc lk: changed values for input cloc k duty cycle under min from 40 to 35 and under max from 60 to 65.
lxt971a 3.3 v dual-speed fast ethernet transceiver 10 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 11 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 1. lxt971a block diagram tx_en rx_er crs power supply management / mode select logic addr<4:0> mdio mdc tx_er rxdv tpfon tpfop tpfin tpfip refclk vcc gnd col rx_clk tx_clk led/cfg<3:1> txd<3:0> decoder & descrambler + - + - serial-to- parallel converter scrambler & encoder parallel/serial converter carrier sense data valid error detect auto negotiation manchester decoder manchester encoder 10 100 10 100 media select tp driver tp/fiber out ecl driver register set register set clock generator + - 100fx + - 10bt collision detect clock generator tx pcs osp ? adaptive eq with baseline wander cancellation osp ? slicer osp ? pulse shaper rxd<3:0> + - 100tx tp/fiber in mddis txslew<1:0> rx pcs pwrdwn jtag 5 tdio tms tck trst sd/tp reset mdint
lxt971a 3.3v dual-speed fast ethernet transceiver 12 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 1.0 pin assignments figure 2. lxt971a 64-ball pbga assignments mdint crs txd3 txd0 rx_er vccd rx_dv rxd0 ref clk/xi col txd2 tx_en tx_er rx_ clk n/c rxd1 xo reset gnd txd1 tx_ clk gnd n/c rxd2 tx slew0 tx slew1 mddis gnd vccio rxd3 n/c mdio addr0 addr1 gnd gnd vccio led/ cfg1 mdc pwr dwn addr3 addr2 gnd gnd tdi tms led/ cfg2 led/ cfg3 addr4 sd/tp vcca vcca tdo tck gnd gnd rbias tpfop tpfon tpfip tpfin trst sleep pause 2 3 4 5 6 7 8 a b c d e f g h a b c d e f g h 1 2 3 4 5 6 7 8 1
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 13 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 3. lxt971a 64-pin lqfp assignments rxd0 rbias 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 refclk/xi xo mddis reset txslew0 txslew1 gnd vccio n/c n/c gnd addr0 addr1 addr2 addr3 addr4 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gn d tpfop tpfon vcca vcca tpfip tpfin gn d sd/tp tdi tdo tms tck trst sl eep 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rxd1 rxd2 rxd3 n/c mdc mdio gnd vccio pwrdwn led/cfg1 led/cfg2 led/cfg3 gnd gnd pause mdin t crs col gnd txd3 txd2 txd1 txd0 tx_en tx_c lk tx_er rx_er rx_clk vccd gnd rx_dv 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 lxt971alc xx xxxxxx xxxxxxxx part # lot # fpo # rev #
lxt971a 3.3v dual-speed fast ethernet transceiver 14 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 1. lqfp numeric pin list pin symbol type reference for full description 1 refclk/xi input table 4 on page 18 2 xo output table 4 on page 18 3 mddis input table 2 on page 16 4 reset input table 4 on page 18 5 txslew0 input table 4 on page 18 6 txslew1 input table 4 on page 18 7gnd ? table 5 on page 19 8 vccio ? table 5 on page 19 9n/c ? table 4 on page 18 10 n/c ? table 4 on page 18 11 gnd ? table 5 on page 19 12 addr0 input table 4 on page 18 13 addr1 input table 4 on page 18 14 addr2 input table 4 on page 18 15 addr3 input table 4 on page 18 16 addr4 input table 4 on page 18 17 rbias analog input table 4 on page 18 18 gnd ? table 5 on page 19 19 tpfop output table 3 on page 17 20 tpfon output table 3 on page 17 21 vcca ? table 5 on page 19 22 vcca ? table 5 on page 19 23 tpfip input table 3 on page 17 24 tpfin input table 3 on page 17 25 gnd ? table 5 on page 19 26 sd/tp input table 3 on page 17 27 tdi input table 6 on page 19 28 tdo output table 6 on page 19 29 tms input table 6 on page 19 30 tck input table 6 on page 19 31 trst input table 6 on page 19 32 sleep input table 4 on page 18 33 pause input table 4 on page 18 34 gnd ? table 5 on page 19 35 gnd ? table 5 on page 19 36 led/cfg3 i/o table 7 on page 19
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 15 document #: 249414 revision #: 002 rev. date: august 7, 2002 37 led/cfg2 i/o table 7 on page 19 38 led/cfg1 i/o table 7 on page 19 39 pwrdwn input table 4 on page 18 40 vccio ? table 5 on page 19 41 gnd ? table 5 on page 19 42 mdio i/o table 2 on page 16 43 mdc input table 2 on page 16 44 n/c ? table 4 on page 18 45 rxd3 output table 2 on page 16 46 rxd2 output table 2 on page 16 47 rxd1 output table 2 on page 16 48 rxd0 output table 2 on page 16 49 rx_dv output table 2 on page 16 50 gnd ? table 5 on page 19 51 vccd ? table 5 on page 19 52 rx_clk output table 2 on page 16 53 rx_er output table 2 on page 16 54 tx_er input table 2 on page 16 55 tx_clk output table 2 on page 16 56 tx_en input table 2 on page 16 57 txd0 input table 2 on page 16 58 txd1 input table 2 on page 16 59 txd2 input table 2 on page 16 60 txd3 input table 2 on page 16 61 gnd ? table 5 on page 19 62 col output table 2 on page 16 63 crs output table 2 on page 16 64 mdint open drain table 2 on page 16 table 1. lqfp numeric pin list (continued) pin symbol type reference for full description
lxt971a 3.3v dual-speed fast ethernet transceiver 16 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 2.0 signal descriptions note: intel recommends that all inputs and multi-functi on pins be tied to the inactive states and all outputs be left floating, if unused. table 2. lxt971a mi i signal descriptions pbga pin# lqfp pin# symbol type 1 signal description data interface pins a3 b3 c4 a4 60 59 58 57 txd3 txd2 txd1 txd0 i transmit data . txd is a bundle of parallel data signals that are driven by the mac. txd<3:0> transitions synchronously with respect to the tx_clk. txd<0> is the least significant bit. b4 56 tx_en i transmit enable . the mac asserts this signal when it drives valid data on txd. this signal must be synchronized to tx_clk. c5 55 tx_clk o transmit clock . tx_clk is sourced by the phy in both 10 and 100 mbps operations. 2.5 mhz for 10 mbps operation, 25 mhz for 100 mbps operation. d6 c8 b8 a8 45 46 47 48 rxd3 rxd2 rxd1 rxd0 o receive data . rxd is a bundle of parallel signals that transition synchronously with respect to the rx_clk. rxd<0> is the least significant bit. a7 49 rx_dv o receive data valid . the lxt971a asserts this signal when it drives valid data on rxd. this output is synchronous to rx_clk. a5 53 rx_er o receive error . signals a receive error condition has occurred. this output is synchronous to rx_clk. b5 54 tx_er i transmit error . signals a transmit error condition. this signal must be synchronized to tx_clk. b6 52 rx_clk o receive clock . 25 mhz for 100 mbps operation, 2.5 mhz for 10 mbps operation. refer to ?clock requirements? on page 26 in section 3.0, ?functional description? . b2 62 col o collision detected . the lxt971a asserts this output when a collision is detected. this output remains high for the duration of the collision. this signal is asynchr onous and is inactive during full- duplex operation. a2 63 crs o carrier sense . during half-duplex operation (register bit 0.8 = 0), the lxt971a asserts this output when either transmitting or receiving data packets. during full-duplex operation (register bit 0.8 = 1), crs is asserted only duri ng receive. crs assertion is asynchronous with respect to rx_clk. crs is de-asserted on loss of carrier, synchronous to rx_clk. 1. type column coding: i = input, o = output, a = analog, od = open drain
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 17 document #: 249414 revision #: 002 rev. date: august 7, 2002 mii control interface pins d3 3 mddis i management disable . when mddis is high, the mdio is disabled from read and write operations. when mddis is low at power-up or reset, the hardware control interface pins control only the init ial or ?default? values of their respective register bits. after t he power-up/reset cycle is complete, bit control reverts to the mdio serial channel. e7 43 mdc i management data clock . clock for the mdio serial data channel. maximum frequency is 8 mhz. d8 42 mdio i/o management data input/output . bidirectional serial data channel for phy/sta communication. a1 64 mdint od management data interrupt . when register bit 18.1 = 1, an active low output on this pin indicates status change. interrupt is cleared by reading register 19. table 3. lxt971a network interface signal descriptions pbga pin# lqfp pin# symbol type 1 signal description h2 h3 19 20 tpfop tpfon o twisted-pair/fiber outputs, positive & negative. during 100base-tx or 10base-t operation, tpfop/n pins drive 802.3 compliant pulses onto the line. during 100base-fx operation, tpfo p/n pins produce differential lvpecl outputs for fiber transceivers. h4 h5 23 24 tpfip tpfin i twisted-pair/fiber input s, positive & negative. during 100base-tx or 10base-t operation, tpfip/n pins receive differential 100base-tx or 10base-t signals from the line. during 100base-fx operation, tpfip/n pins receive differential lvpecl inputs from fiber transceivers. g2 26 sd/tp i signal detect 2 : dual function input depending on the state of the device. reset and power-up. media mode selection: tie high for fx mode (register bit 16.0 = 1) tie low for tp mode (register bit 16.0 = 0) normal operation (fx mode): sd input from the fiber transceiver. normal operation (tp mode): tie to gnd (uses an internal pull- down). 1. type column coding: i = input, o = output, a = analog, od = open drain 2. for standard digital loopback testing (register bit 0. 14) in fx mode, the sd pin should be tied to an lvpecl logic high (2.4 v). table 2. lxt971a mii signal descriptions (continued) pbga pin# lqfp pin# symbol type 1 signal description 1. type column coding: i = input, o = output, a = analog, od = open drain
lxt971a 3.3v dual-speed fast ethernet transceiver 18 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 4. lxt971a miscellan eous signal descriptions pbga pin# lqfp pin# symbol type 1 signal description d1 d2 5 6 txslew0 txslew1 i tx output slew controls 0 and 1 . these pins select the tx output slew rate (rise and fall time) as follows: txslew1 txslew0 slew rate (rise and fall time) 0 0 3.0 ns 0 1 3.4 ns 1 0 3.9 ns 1 1 4.4 ns c2 4 reset i reset . this active low input is or?ed with the control register reset bit (register bit 0.15). the lxt971a reset cycle is extended to 258 s (nominal) after reset is de- asserted. g1 f1 f2 e2 e1 16 15 14 13 12 addr4 addr3 addr2 addr1 addr0 i i i i i address <4:0> . sets device address. h1 17 rbias ai bias . this pin provides bias current for the internal circuitry. must be tied to ground through a 22.1 k ? , 1% resistor. h8 33 pause i pause . when set high, the lxt971a advertises pause capabilities during auto-negotiation. h7 32 sleep i sleep . when set high, this pin enables the lxt971a to go into a low-power sleep mode. the value of this pin can be overridden by register bit 16.6 when in managed mode. e8 39 pwrdwn i power down . when set high, this pin puts the lxt971a in a power-down mode. b1 c1 1 2 refclk/xi xo i o crystal input and output . a 25 mhz crystal oscillator circuit can be connected across xi and xo. a clock can also be used at xi. refer to ?clock requirements? on page 26 in the functional description section. b7, c7 d7 9, 10 44 n/c - no connection . these pins are not used and should not be terminated. 1. type column coding: i = input, o = output, a = analog, od = open drain.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 19 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 5. lxt971a power supply signal descriptions pbga pin# lqfp pin# symbol type signal description a6 51 vccd ? digital power. requires a 3.3v power supply. d4, e3 e4, f3 f4, c6, c3, g7, g8 7, 11, 18, 25, 34, 35, 41, 50, 61 gnd ? ground. e5, d5 8, 40 vccio ? mii power. requires either a 3.3v or a 2.5v supply. must be supplied from the same source used to power the mac on the other side of the mii. g3, g4 21, 22 vcca ? analog power. requires a 3.3v power supply. table 6. lxt971a jtag test signal descriptions pbga pin# lqfp pin# symbol type 1 signal description f5 27 tdi 2 i test data input . test data sampled with respect to the rising edge of tck. g5 28 tdo 2 o test data output . test data driven with respect to the falling edge of tck. f6 29 tms 2 i test mode select . g6 30 tck 2 i test clock . test clock input sourced by ate. h6 31 trst 2 i test reset . test reset input sourced by ate. 1. type column coding: i = input, o = output, a = analog, od = open drain. 2. if jtag port is not used, these pins do not need to be terminated. table 7. lxt971a led signal descriptions pbga pin# lqfp pin# symbol type 1 signal description e6 f7 f8 38 37 36 led/cfg1 led/cfg2 led/cfg3 i/o led drivers 1-3. these pins drive led indicators. each led can display one of several available status conditions as selected by the led configuration register (refer to table 56 on page 85 for details). configuration inputs 1-3. these pins also provide initial configuration settings (refer to table 9 on page 30 for details). 1. type column coding: i = input, o = output, a = analog, od = open drain. 2. pull-up/pull-down resistors of 10 k can be im plemented if leds are used in the design.
lxt971a 3.3v dual-speed fast ethernet transceiver 20 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 8. lxt971a pin types and modes modes rxd 0-3 rxdv tx/rx clks output rxer output col output crs output txd 0-3 input txen input txer input hwreset dl dl dh dl dl dl ipld ipld ipld sftpwrdn dl dl active dl dl dl ipld ipld ipld hwpwrdn high z high z high z high z high z high z high z high z high z isolate hz w/ ipld hz w/ ipld hz w/ ipld hz w/ ipld hz w/ ipld hz w/ ipld ipld ipld ipld sleep dl dl dl dl dl dl ipld ipld ipld 1. a high z (high impedance) or three-state determines when the device is drawing a current of less than 20 na. a high z with pld (high impedance with pull-do wn) state determines when the device is drawing a current of less than 20 a. 2. dl = driven low (logic 0), dh = driven high (logic 1), ipld = internal pull-down (weak)
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 21 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.0 functional description 3.1 introduction the lxt971a is a single-port fast ethernet 10/ 100 transceiver that supports 10 mbps and 100 mbps networks and complies with all applicab le requirements of ieee 802.3. the lxt971a directly drives either a 100base-tx line (up to 140 meters) or a 10base-t line (up to 185 meters). the device also supports 100base-fx operation via a low voltage pecl (lvpecl) interface. 3.1.1 comprehensive functionality the lxt971a provides a standard media indepe ndent interface (mii) for 10/100 macs. the lxt971a performs all functions of the physi cal coding sublayer (pcs ) and physical media attachment (pma) sublayer as defined in the ieee 802.3 100base-x standard. this device also performs all functions of the physical medi a dependent (pmd) sublayer for 100base-tx connections. the lxt971a reads its configuration pins on power-up to check for forced operation settings. if not configured for forced oper ation, the device uses auto-negotiation/parallel detection to automatically determine line operating conditions. if the phy device on the other side of the link supports auto-negotiation, the lxt971a auto-negotiates with it using fast link pulse (flp) bursts. if the phy partner does not support auto-negotiation, the lxt971a automatically detects the presence of either li nk pulses (10 mbps phy) or idle sy mbols (100 mbps phy) and sets its operating conditions accordingly. the lxt971a provides half-duplex and full-dup lex operation at 100 mbps and 10 mbps. 3.1.2 osp? architecture the lxt971a incorporates high-efficiency op timal signal processing? design techniques, combining the best properties of digital and anal og signal processing to produce a truly optimal device. the receiver utilizes decision feedback equalizati on to increase noise and cross-talk immunity by as much as 3 db over an ideal all-analog equalizer. using osp mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calcula tion truncation errors found in traditional dsp-based receivers (typically complex dsp engines with a/d converters). this results in improved receiver noise and cross-talk performance. the osp signal processing scheme also requires substantially less computational logic than traditional dsp-based designs. this lowers pow er consumption and also reduces the logic switching noise generated by dsp engines. this logi c switching noise can be a considerable source of emi generated on the device?s power supplies. the osp-based lxt971a provides improved data recovery, emi performance and low power consumption.
lxt971a 3.3v dual-speed fast ethernet transceiver 22 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.2 network media / protocol support the lxt971a supports both 10base-t and 100b ase-tx ethernet over twisted-pair, or 100 mbps ethernet over fiber media (100base-fx). 3.2.1 10/100 netw ork interface the network interface port consists of five external pins (two differential si gnal pairs and a signal detect pin). the i/o pins are shared between twisted-pair (tp) and fiber. refer to figure 3 on page 13 for specific pin assignments. the lxt971a output drivers generate either 100base-tx, 10base-t, or 100base-fx output. when not transmitting data, the lxt971a generate s 802.3-compliant link pulses or idle code. input signals are decoded either as a 100base- tx, 100base-fx, or 10base-t input, depending on the mode selected. auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. 3.2.1.1 twisted-pair interface the lxt971a supports either 100base-tx or 10base-t connections over 100 ?, category 5, unshielded twisted pair (utp) cable. when operating at 100 mbps, the lxt971a continuously transmits and receives mlt3 symbols. when not transmitting data, the lxt971a generates ?idle? symbols. during 10 mbps operation, manchester-encoded data is exchanged. when no data is being exchanged, the line is left in an idle state. link pulses are transmitted periodically to keep the link up. only a transformer, rj-45 connector, load resist or, and bypass capacitors are required to complete this interface. on the transmit side, the lxt971a has an active in ternal termina tion and does not require external termination resistors. intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external emi filters. four slew rate settings (refer to table 4 on page 18 ) allow the designer to match the output wave form to the magnetic characteristics. on the receive side, the internal impedance is high eno ugh that it has no practical effect on the external termination circuit. 3.2.1.2 fiber interface the lxt971a fiber port is designed to interface with common industry-standard fiber modules. it incorporates a low voltage pecl interface that complies with the ansi x3.166 standard for seamless integration. fiber mode is selected through register bit 16.0 by the following two methods: 1. drive the sd input to a valu e greater than 600 mv during power-up and reset states (all lvpecl signaling levels from a fiber transceiver are acceptable). 2. configure register bit 16.0 = 1 through the mdio interface.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 23 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.2.1.3 fault detection and reporting the lxt971a supports two fault detection and reporting mechanisms. ?remote fault? refers to a mac-to-mac communication function that is essentially transparent to phy layer devices. it is used only during auto-negotiation, and is applicable only to twisted-pair links. ?far-end fault? is an optional pma-layer function that may be embedded within phy devices. the lxt971a supports both functions (see section 3.2.1.3.1 and section 3.2.1.3.2 ). 3.2.1.3.1 remote fault register bit 4.13 in the auto-negotiation advertis ement register is reserved for remote fault indications. it is typically used when re-startin g the auto-negotiation se quence to indicate to the link partner that the link is down because the advertising device detected a fault. when the lxt971a receives a remote fault indicat ion from its partner dur ing auto-negotiation it does the following: ? sets register bit 5.13 in the link partner base page ability register, and ? sets the remote fault register bit 1.4 in the mii status register to pass this information to the local controller. 3.2.1.3.2 100base-fx far-end fault the sd/tp pin monitors signal quality during normal operation in fiber mode. if the signal quality degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via the sd/tp pin. loss of signal quality blocks any fibe r data from being received and causes a link loss. if the lxt971a detects a signal fault condition, it can transmit the far-end fault indication (fefi) over the fiber link. the fefi consists of 84 consecutive ones followed by a single zero. this pattern must be repeated at least three times. the lxt971a transmits the far-end fault code a minimum of three times if all the following conditions are true: ? fiber mode is selected. ? fault code transmission is enabled (register bit 16.2 = 1). ? either signal detect in dicates no signal or the receive pll cannot lock. ? loopback is not enabled. 3.2.2 mii data interface the lxt971a supports a standard media independen t interface (mii). the mii consists of a data interface and a management interface. the mii da ta interface passes data between the lxt971a and a media access controller (mac). separate parallel buses are prov ided for transmit and receive. this interface operates at either 10 mbps or 100 mbps. the speed is set automatically, once the operating conditions of the network link have been determined. refer to ?mii operation? on page 32 for additional details. 3.2.2.1 increased mii drive strength a higher media independen t interface (mii) drive stre ngth may be desired in some designs to drive signals over longer pcb trace le ngths, or over high-capacitive lo ads, through mu ltiple vias, or through a connector. the mii drive strength in the lxt971a can be increased by setting register
lxt971a 3.3v dual-speed fast ethernet transceiver 24 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 bit 26.11 through software control. setting register bit 26.11 = 1 through the mdc/mdio interface sets the mii pins (rxd[0:3], rx_dv, rx_clk, rx_er, col, crs, and tx_clk) to a higher drive strength. 3.2.3 configuration management interface the lxt971a provides both an mdio interface and a hardware control interface for device configuration and management. 3.2.3.1 mdio management interface the lxt971a supports the ieee 802.3 mii ma nagement interface al so known as the management data input/output (m dio) interface. this interface allows upper-layer devices to monitor and control the state of the lxt971a. the mdio inte rface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. some registers are required and their functions are defined by the ieee 802.3 standard. the lxt971a also supports additional registers for expanded functionality. the lxt971a supports multiple internal registers, each of which is 16 bi ts wide. specific register bits are referenced using an ?x.y? notation, where x is the register number (0-31) and y is the bit number (0-15). the physical interface consists of a data line (m dio) and clock line (mdc). operation of this interface is controlled by the mddis input pin. when mddis is high, the mdio read and write operations are disabled and the hardware control interface provides primary configuration control. when mddis is low, the mdio port is enable d for both read and write operations and the hardware control interface is not used. 3.2.3.1.1 mdio addressing the protocol allows one controller to comm unicate with multiple lxt971a chips. pins addr<4:0> determine the chip address. 3.2.3.1.2 mdio frame structure the physical interface consists of a data line (mdi o) and clock line (mdc). the frame structure is shown in figures 4 and 5 (read and write). mdio in terface timing is shown in table 38 on page 69. figure 4. management interface read frame structure mdc mdio (read) 32 "1"s 0110 preamble st op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data write read d15 d14 d1 d0 idle high z
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 25 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.2.3.1.3 mii interrupts the lxt971a provides a single interrupt pin (mdint ). interrupt logic is shown in figure 6 . the lxt971a also provides two dedicated interrupt re gisters. register 18 provides interrupt enable and mask functions and register 19 provides interrupt status. setting register bit 18.1 = 1, enables the device to request interrupt via the mdint pin. an active low on th is pin indicates a status change on the lxt971a. interrupts may be caused by four conditions: ? auto-negotiation complete ? speed status change ? duplex status change ? link status change 3.2.3.2 hardware control interface the lxt971a provides a hardware control interf ace for applications where the mdio is not desired. the hardware control interface uses the th ree led driver pins to set device configuration. refer to the hardware configuration settings section on page 30 for additional details . figure 5. management interface write frame structure mdc mdio (write) 32 "1"s 0101 preamble st op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 d0 data idle idle write figure 6. interrupt logic nand even x mask reg even x status reg force interrupt interrupt enable and or interrupt pin (mdint)
lxt971a 3.3v dual-speed fast ethernet transceiver 26 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.3 operating requirements 3.3.1 power requirements the lxt971a requires three power supply inputs (vccd, vcca, and vccio). the digital and analog circuits require 3.3v supplies (vccd and vcca). these inputs may be supplied from a single source. each supply input must be de-coupled to ground. an additional supply may be used for the mii (vccio). the supply may be either +2.5v or +3.3v. also, the inputs on the mii interface are tole rant to 5v signals from the controller on the other side of the mii interface. refer to table 20 on page 57 for mii i/o characteristics. as a matter of good practice, these supplies should be as clean as possible. 3.3.2 clock requirements 3.3.2.1 external crystal/oscillator the lxt971a requires a reference clock input that is used to generate transmit signals and recover receive signals. it may be provid ed by either of two methods: by connecting a crystal across the oscillator pins (xi and xo), or by connecting an external clock source to pin xi. the connection of a clock source to the xi pin requires the xo pi n to be left open. a crystal-based clock is recommended over a derived clock (i.e., pll-based) to minimize transmit jitter. refer to the lxt971a/972a design and layout guide fo r a list of recommend ed clock sources. a crystal is typically used in nic applications. an external 25 mhz clock source, rather than a crystal, is frequently used in switch applications. refer to table 21 on page 57 for clock timing requirements. 3.3.2.2 mdio clock the mii management channel (mdio) also requires an external clock. the managed data clock (mdc) speed is a maximum of 8 mhz. refer to table 38 on page 69 for details. 3.4 initialization when the lxt971a is first powered on, reset, or encounters a link failure state, it checks the mdio register configuration bits to determine the line speed and operating conditions to use for the network link. the conf iguration bits may be set by the hard ware control or mdio interface as shown in figure 7 . 3.4.1 mdio control mode in the mdio control mode, the lxt971a reads th e hardware control interface pins to set the initial (default) values of the mdio registers. once the initial va lues are set, bit control reverts to the mdio interface.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 27 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.4.2 hardware control mode in the hardware control mode, lxt971a disables direct write operations to the mdio registers via the mdio interface. on power-up or hardware reset the lxt971a reads the hardware control interface pins and sets the mdio registers accordingly. the following modes ar e available using either hardwa re control or mdio control: ? force network link to 100fx (fiber). ? force network link operation to: ? 100base-tx, full-duplex. ? 100base-tx, half-duplex. ? 10base-t, full-duplex. ? 10base-t, half-duplex. ? allow auto-negotiation/parallel-detection. when the network link is forced to a specific configuration, the lxt971a immediately begins operating the network interface as commanded. when auto-negotiation is enabled, the lxt971a begins the auto-negotiation/parallel-detection operation.
lxt971a 3.3v dual-speed fast ethernet transceiver 28 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.4.3 reduced power modes the lxt971a offers two power-down modes and a sleep mode. 3.4.3.1 hardware power down the hardware power-down mode is controlled by the pwrdwn pin. when pwrdwn is high, the following conditions are true: ? the lxt971a network port and clock are shut down. ? all outputs are three-stated. ? all weak pad pull-up and pull-down resistors are disabled. ? the mdio registers are not accessible. figure 7. initialization sequence mddis voltage level? high low mdio control mode hardware control mode disable mdio read and write operations reset mdio registers to values read at h/w control interface at last hardware reset mdio controlled operation (mdio writes enabled) power-up or reset initialize mdio registers read h/w control interface software reset? yes no
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 29 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.4.3.2 software power down software power-down control is provided by register bit 0.11 in the control register (refer to table 43 on page 74 ). during soft power-down, the following conditions are true: ? the network port is shut down. ? the mdio registers remain accessible. 3.4.3.3 sleep mode the lxt971a supports a power-sav ing sleep mode. sleep mode is enabled when sleep is asserted via pin 32(lqfp)/h7(pbga). the value of pin 32/h7 can be overridden by register bit 16.6 when in managed mode as shown in table 4 on page 18 . the lxt971a enters into sleep mode when sleep is enabled and no energy is det ected on the twisted-pair input for 1-3 seconds (the time is controlled by register bits 16.4:3 in the configuration register, with a default of 3.04 seconds). during this mode, the lxt971a still responds to management transactions (mdc/mdio). in this mode the power consumption is minimized, and the supply current is reduced below the maximum value given in table 18 on page 56 . if the lxt971a detects activity on the twisted-pair inputs, it comes out of the sleep state and check for link. if no link is detected in 1-3 seconds (programmable) it reverts back to the low power sleep state. note: sleep mode is not functional in fiber network applications. 3.4.4 reset the lxt971a provides both hardware and software resets. configuration control of auto- negotiation, speed, and d uplex mode selection is handled differently for each. during a hardware reset, auto-negotiation and speed configuration settings are read in from pins (refer to table 9 on page 30 for pin settings and to table 43 on page 74 for register bit definitions). during a software reset (0.15 = 1), these bit settings are not re-read from the pins. they revert back to the values that were read in during the last ha rdware reset. therefore, any changes to pin values made since the last hardware reset is not detected during a software reset. during a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. during a software reset (0.15 = 1) the registers ar e available for reading. the reset bit should be polled to see when the part has completed reset (0.15 = 0).
lxt971a 3.3v dual-speed fast ethernet transceiver 30 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.4.5 hardware configuration settings the lxt971a provides a hardware option to set the initial device configuration. the hardware option uses the three led driver pins. this provides three control bits, as listed in table 9 . the led drivers can operate as either open-drain or open-source circuits as shown in figure 8 . figure 8. hardware configuration settings table 9. hardware configuration settings desired mode led/cfg n pin settings 1 resulting register bit values control register an advertisement registers auto- neg speed (mbps) duplex 1 2 3 auto- neg 0.12 speed 0.13 fd 0.8 100fd 4.8 100tx 4.7 10fd 4.6 10t 4.5 disabled 10 half low low low 0 0 0 n/a auto-negotiation adver- tisement full low low high 1 100 half low high low 1 0 full low high high 1 enabled 100 only half high low low 11 00 100 full high low high 1 1 1 0 0 10/100 half only high high low 0 0 1 0 1 full or half high high high 1 1 1 1 1 1. refer to table 7 on page 19 for led/cfg pin assignments. configuration bit = 1 configuration bit = 0 led/cfg pin led/cfg pin 3.3 v 1. the led/cfg pins auto matically adjust their polarity upon power-up or reset. 2. unused leds may be implemented with pull-up/ pull-down resistors of 10 k.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 31 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.5 establishing link see figure 9 for an overview of link establishment. 3.5.1 auto-negotiation if not configured for forced operation, the lxt971a attempts to auto-negotiate with its link partner by sending fast link pulse (f lp) bursts. each burst consists of up to 33 link pulses spaced 62.5 s apart. odd link pulses (clock pulses) are alwa ys present. even link pulses (data pulses) may be present or absent to indicate a ?1? or a ?0?. each flp burst exchanges 16 bits of data, which are referred to as a ?link code word ?. all devices that support auto -negotiation must implement the ?base page? defined by ieee 802.3 (registers 4 and 5). lxt971a also supports the optional ?next page? function as described in tables 50 and 51 on page 80 (registers 7 and 8). 3.5.1.1 base page exchange by exchanging base pages, the lxt971a and its link partner communicate their capabilities to each other. both sides must receive at least thr ee identical base pages fo r negotiation to continue. each side identifies the highest common capabilities that both si des support and configures itself accordingly. 3.5.1.2 next page exchange additional information, above that required by base page exchange is also sent via ?next pages?. the lxt971a fully supports the ieee 802.3ab method of negotiation via next page exchange. 3.5.1.3 controlling auto-negotiation when auto-negotiation is controlled by so ftware, the following steps are recommended: ? after power-up, power-down, or reset, the power-down recovery time, as specified in table 40 on page 70 , must be exhausted before proceeding. ? set the auto-negotiation advertisement register bits. ? enable auto-negotiation (set mdio register bit 0.12 = 1). 3.5.2 parallel detection for the parallel detection feature of auto-negot iation, the lxt971a also monitors for 10base-t normal link pulses (nlp) and 100base-tx idle symbols. if either is detected, the device automatically reverts to the corresponding operating mode. parallel detection allows the lxt971a to communicate with devices that do not support auto-negotiation.
lxt971a 3.3v dual-speed fast ethernet transceiver 32 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.6 mii operation the lxt971a device implements the media independent interface (mii) as defined in the ieee 802.3 standard. separate channels are provide d for transmitting data from the mac to the lxt971a (txd), and for passing data received from the line (rxd) to the mac. each channel has its own clock, data bus, and control signals. ni ne signals are used to pass received data to the mac: rxd<3:0>, rx_clk, rx_dv, rx_er, col, and crs. seven signals are used to transmit data from the mac: txd<3:0>, tx_clk, tx_en, and tx_er. the lxt971a supplies both clock signals as well as separate outputs for carrier sense and collision. data transmission across the mii is normally implemented in 4-bit-wide nibbles. 3.6.1 mii clocks the lxt971a is the master clock source for da ta transmission and supplies both mii clocks (rx_clk and tx_clk). it automatically sets th e clock speeds to match link conditions. when the link is operating at 100 mbps , the clocks are set to 25 mhz. when the link is operating at 10 mbps, the clocks are set to 2.5 mhz. figures 10 through 12 show the clock cycles for each mode. the transmit data and control signals must always be synchronized to tx_clk by the mac. the lxt971a samples these signals on the rising edge of tx_clk. figure 9. link establishment overview check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link up? no yes power-up, reset, waking up from sleep mode, or link failure disable auto-negotiation 0.12 = 0 0.12 = 1
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 33 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.6.2 transmit enable the mac must assert tx_en the sa me time as the first nibble of preamble, and de-assert tx_en after the last bit of the packet. 3.6.3 receive data valid the lxt971a asserts rx_dv when it receives a valid packet. timing ch anges depend on line operating speed: ? for 100base-tx links, rx_dv is asserted from th e first nibble of preambl e to the last nibble of the data packet. ? for 10bt links, the entire preambl e is truncated. rx_dv is asserted with the first nibble of the start of frame delimiter (sfd) ?5d? and remains asserted until the end of the packet. 3.6.4 carrier sense carrier sense (crs) is an asynchronous output . it is always generated when a packet is received from the line and in half-duplex mode when a packet is transmitted. table 10 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. carrier sense is not generated when a pack et is transmitted and in full-duplex mode. 3.6.5 error signals when lxt971a is in 100 mbps mode and receives an invalid symbol from the network, it asserts rx_er and drives ?1110? on the rxd pins. when the mac asserts tx_er, the lxt971a drives ?h? symbols out on the tpfop/n pins. 3.6.6 collision the lxt971a asserts its collision signal, asynchro nously to any clock, whenever the line state is half-duplex and the transmitter and r eceiver are active at the same time. table 10 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
lxt971a 3.3v dual-speed fast ethernet transceiver 34 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.6.7 loopback the lxt971a provides two loopback functions, operational and test (see table 10 ). loopback paths are shown in figure 13 . figure 10. 10base-t clocking figure 11. 100base-x clocking figure 12. link down clock transition rx_clk (sourced by lxt971a) 2.5 mhz during auto-negotiation and 10base-t data & idle tx_clk (sourced by lxt971a) 2.5 mhz during auto-negotiation and 10base-t data & idle constant 25 mhz xi rx_clk (sourced by lxt971a) 2.5 mhz during auto-negotiation tx_clk (sourced by lxt971a) constant 25 mhz xi 25 mhz once 100base-x link established 2.5 mhz during auto-negotiation 25 mhz once 100base-x link established any clock 2.5 mhz clock clock transition time will not exceed 2x the nominal clock period: 10 mbps = 2.5 mhz 100 mbps = 25 mhz link-down condition/auto-negotiate enabled rx_clk tx_clk
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 35 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.6.7.1 operational loopback operational loopback is provided for 10 mbps ha lf-duplex links when register bit 16.8 = 0. data transmitted by the mac (txdata) is looped back on the receive side of the mii (rxdata). operational loopback is not provided for 100 m bps links, full-duplex links, or when 16.8 = 1. 3.6.7.2 test loopback a test loopback function is provided for diagnostic testing of the lxt971a. during test loopback, twisted-pair and fiber interfaces are disabled. da ta transmitted by the mac is internally looped back by the lxt971a and returned to the mac. test loopback is available fo r both 100base-tx and 10base-t operation, and is enabled by setting the following register bits: ? register bit 0.14 = 1 ? register bit 0.8 = 1 (full-duplex) ? register bit 0.12 = 0 (disable auto-negotiation). test loopback is also available for 100base-fx operation. test loopback in this mode is enabled by setting register bit 0.14 = 1 and tying the sd input to an lvpecl logic high value (2.4 v). figure 13. loopback paths 10t loopback digital block mii tx driver 100x loopback fx driver analog block lxt971a
lxt971a 3.3v dual-speed fast ethernet transceiver 36 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.7 100 mbps operation 3.7.1 100base-x ne twork operations during 100base-x operation, th e lxt971a transmits and recei ves 5-bit symbols across the network link. figure 14 shows the structure of a standard frame packet. when the mac is not actively transmitting data, the lxt971a sends out idle symbols on the line. in 100base-tx mode, the lxt971a scrambles and transmits the data to the network using mlt- 3 line code ( figure 15 on page 37 ). mlt-3 signals recei ved from the network are de-scrambled, decoded, and sent across the mii to the mac. in 100base-fx mode, the lxt971 a transmits and receives nrzi signals across the lvpecl interface. an external 100fx transceiver module is required to complete the fiber connection. to enable 100base-fx operation, auto-negotiation must be disabled and fx selected. table 10. carrier sense, loopback, and collision conditions speed duplex condition carrier sense test 1 loopback operational loopback collision 100 mbps full-duplex receive only yes no none half-duplex transmit or receive no no transmit and receive 10 mbps full-duplex receive only yes no none half-duplex, register bit 16.8 = 0 transmit or receive yes yes transmit and receive half-duplex, register bit 16.8 = 1 transmit or receive no no transmit and receive 1. test loopback is enabled when 0.14 = 1 figure 14. 100base-x frame format p0 p1 p6 sfd 64-bit preamble (8 octets) start-of-frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet length (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code-groups end-of-stream delimiter (esd) ifg replaced by /j/k/ code-groups start-of-stream delimiter (ssd)
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 37 document #: 249414 revision #: 002 rev. date: august 7, 2002 as shown in figure 14 on page 36 , the mac starts each transmissi on with a preamble pattern. as soon as the lxt971a detects the st art of preamble, it transmits a start-of-stream delimiter (ssd, symbols j and k) to the network. it then encodes and transmits the rest of the packet, including the balance of the preamble, the sfd, packet data, and crc. once the packet ends, the lxt971a transmits the end-of- stream delimiter (esd, symbols t and r) and then returns to transmitting idle symbols. 4b/5b coding is shown in table 11 on page 40 . figure 16 shows normal reception with no errors. when the lxt 971a receives invalid symbols from the line, it asserts rx_er as shown in figure 17 . figure 15. 100base-tx data path s0 s1 s2 s3 s4 parallel to serial serial to parallel mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scrambler bypass data flow s0 s1 s2 s3 s4 standard data flow d0 d1 d2 d3 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble figure 16. 100base-tx reception with no errors figure 17. 100base-tx reception with invalid symbol rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da da da crc crc crc crc rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da xx xx xx xx xx xx xx xx xx xx
lxt971a 3.3v dual-speed fast ethernet transceiver 38 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.7.2 collision indication figure 18 shows normal transmission. upon detection of a collision, the col output is asserted and remains asserted for the duration of the collision as shown in figure 19 . 3.7.3 100base-x protocol sublayer operations with respect to the 7-layer communications model, the lxt971a is a physical layer 1 (phy) device. the lxt971a implements the physical coding sublayer (pcs), physical medium attachment (pma), and physical medium depe ndent (pmd) sublayers of the reference model defined by the ieee 802.3u standard. the following paragraphs discuss lxt971a operation from the reference model point of view. 3.7.3.1 pcs sublayer the physical coding sublayer (pcs) provides the mii interface, as well as the 4b/5b encoding/ decoding function. for 100base-tx and 100fx operation, the pcs layer provides idle symbols to the pmd-layer line driver as long as tx_en is de-asserted. 3.7.3.1.1 preamble handling when the mac asserts tx_en, the pcs substitutes a /j/k symbol pair, also known as the start-of- stream delimiter (ssd), for the first two nibbles received across th e mii. the pcs layer continues to encode the remaining mii data, following the coding in table 11 , until tx_en is de-asserted. it then returns to supplying idle symbols to the line driver. figure 18. 100base-tx transmission with no errors figure 19. 100base-tx tran smission with collision da da da da da da da da da tx_clk tx_en txd<3:0> crs col pr ea mb le jam tx_clk tx_en txd<3:0> crs col pr ea mb le jam jam jam
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 39 document #: 249414 revision #: 002 rev. date: august 7, 2002 in the receive direction, the pcs layer performs the opposite function, substituting two preamble nibbles for the ssd. 3.7.3.1.2 dribble bits the lxt971a handles dribbles bits in all modes. if one to four dri bble bits are received, the nibble is passed across the mii, and padd ed with ones if necessary. if five to seven dribble bits are received, the second nibble is not sent to the mii bus. figure 20. protocol sublayers encoder/decoder serializer/de-serializer link/carrier detect pcs sublayer pma sublayer mii interface pecl interface fiber transceiver lxt971a 100base-tx 100base-fx scrambler/ de-scrambler pmd sublayer
lxt971a 3.3v dual-speed fast ethernet transceiver 40 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 11. 4b/5b coding code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation data 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 used as inter-stream fill code control 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2 1. the /i/ (idle) code group is s ent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are al ways sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are alwa ys sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 41 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.7.3.2 pma sublayer 3.7.3.2.1 link in 100 mbps mode, the lxt971a establishes a li nk whenever the scrambler becomes locked and remains locked for approximately 50 ms. whenever the scrambler loses lock (receiving less than 12 consecutive idle symbols during a 2 ms window), the link is taken down. this provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. furthermore, 100 mbps idle patterns will not bring up a 10 mbps link. the lxt971a reports link failure via the mii status bits (register bits 1.2 and 17.10) and interrupt functions. link failure causes the lxt971a to re-negotiate if auto-negotiation is enabled. 3.7.3.2.2 link failure override the lxt971a normally transmits data packets only if it detects the link is up. setting register bit 16.14 = 1 overrides this function, allowing the lxt971a to transmit data packets even when the link is down. this feature is prov ided as a diagnostic tool. note that auto-negotiation must be disabled to transmit data pack ets in the absence of link. if auto-negotiation is enabled, the lxt971a automatically transmits flp bursts if the link is down. 3.7.3.2.3 carrier sense for 100base-tx and 100fx links, a start-of-stream delimiter (ssd) or /j/k symbol pair causes assertion of carrier sense (crs). an end-of-stream delimiter (esd) or /t/r symbol pair causes de- assertion of crs. the pma layer also de-asserts crs if idle symbols are received without /t/r; however, in this case rx_er is asserted fo r one clock cycle when crs is de-asserted. usage of crs for interframe gap (ifg) timing is not recommended for the following reasons: invalid undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid table 11. 4b/5b coding (continued) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 1. the /i/ (idle) code group is se nt continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are al ways sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
lxt971a 3.3v dual-speed fast ethernet transceiver 42 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 ? de-assertion time for crs is slightly longer than assertion time. this causes ifg intervals to appear somewhat shorter to the mac than it actually is on the wire. ? crs de-assertion is not aligned with tx_en de-assertion on transmit loopbacks in half- duplex mode. 3.7.3.2.4 receive data valid the lxt971a asserts rx_dv to indicate that the r eceived data maps to valid symbols. however, rxd outputs zeros until the received data is decoded and availabl e for transfer to the controller. 3.7.3.3 twisted-pair pmd sublayer the twisted-pair physical medium dependent (p md) layer provides the signal scrambling and de- scrambling, line coding and decoding (mlt-3 fo r 100base-tx, manchester for 10base-t), as well as receiving, polarity correction, and baseline wander correction functions. scrambler/de-scrambler the purpose of the scrambler is to spread the si gnal power spectrum and further reduce emi using an 11-bit, data-independent po lynomial. the receiver automati cally decodes the polynomial whenever idle symbols are received. scrambler seeding once the transmit data (or idle sy mbols) are properly encoded, they are scrambled to further reduce emi and to spread the power sp ectrum using an 11-bit scramble r seed. five seed bits are determined by the phy addre ss, and the remaining bits are hard coded in the design. scrambler bypass the scrambler/de-scrambler can be bypassed by se tting register bit 16.12 = 1. the scrambler is automatically bypassed when the fiber port is enabled. scrambler bypass is provided for diagnostic and test support. 3.7.3.3.1 baseline wander correction the lxt971a provides a baseline wander correction function which makes the device robust under all network operating conditions. the mlt3 coding scheme used in 100base-tx is by definition ?unbalanced?. this means that the average value of the signal voltage can ?wander? significantly over short time interv als (tenths of seconds). this wa nder can cause receiver errors at long-line lengths (100 meters) in less robust designs. exact characteristics of the wander are completely data dependent. the lxt971a baseline wander co rrection characteristics allow th e device to recover error-free data while receiving worst-case ?kill er? packets over all cable lengths. 3.7.3.3.2 polarity correction the 100base-tx de-scrambler au tomatically detects and correct s for the condition where the receive signal at tpfip and tpfin is inverted.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 43 document #: 249414 revision #: 002 rev. date: august 7, 2002 3.7.3.3.3 programmable slew rate control the lxt971a device supports a slew rate mechanis m whereby one of four pre-selected slew rates can be used. this allows the designer to optimize the output waveform to match the characteristics of the magnetics. the slew rate is determined by the txslew pins as shown in table 4 on page 18 . 3.7.3.4 fiber pmd sublayer the lxt971a provides a low voltage pecl interface for connection to an external 3.3 v or 5.0 v fiber-optic transceiver. (the external transceive r provides the pmd function for fiber media.) the lxt971a uses an nrzi format for the fiber in terface. the fiber interface operates at 100 mbps and does not support 10fl applications. 3.8 10 mbps operation the lxt971a operates as a standard 10base-t transceiver. the lxt971a supports all the standard 10 mbps functions. du ring 10base-t operation, the lx t971a transmits and receives manchester-encoded data across the network link. when the mac is not act ively transmitting data, the lxt971a drives link pulses onto the line. in 10base-t mode, the polynomial scrambler/de -scrambler is inactive. manchester-encoded signals received from the network are decoded by the lxt971a and sent across the mii to the mac. the lxt971a does not support fiber connections at 10 mbps. 3.8.1 10base-t preamble handling the lxt971a offers two options for preamble handling, selected by register bit 16.5. in 10base-t mode when 16.5 = 0, the lxt971a strips the entire preamble off of received packets. crs is asserted coincident with sfd. rx_dv is held low for the duration of the preamble. when rx_dv is asserted, the very first two nibble s driven by the lxt971a are the sfd ?5d? hex followed by the body of the packet. in 10base-t mode with 16.5 = 1, the lxt971a passes the preamble through the mii and asserts rx_dv and crs simultaneously. in 10base-t loopback, the lxt971a loops back whatever the mac transmits to it, including the preamble. 3.8.2 10base-t carrier sense for 10base-t links, crs assertion is based on r eception of valid preamble, and de-assertion on reception of an end-of-frame (e of) marker. register bit 16.7 allows crs de-assertion to be synchronized with rx_dv de-assertion. refer to table 52 on page 81 . 3.8.3 10base-t dribble bits the lxt971a device handles dribbles bits in all modes. if one to fo ur dribble bits are received, the nibble is passed across the mii, pa dded with ones if necessary. if five to seven dribble bits are received, the second nibble is not sent to the mii bus.
lxt971a 3.3v dual-speed fast ethernet transceiver 44 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 3.8.4 10base-t link integrity test in 10base-t mode, the lxt971a always transmits link pulses. when the link integrity test function is enabled (the normal configuration), it monitors the connection for link pulses. once link pulses are detected, data transmission is enable d and remains enabled as long as either the link pulses or data transmission continue. if the link pulses stop, the data transmission is disabled. if the link integrity test function is disabled, the lxt971a transmits to the connection regardless of detected link pulses. the link integrity test function can be disabled by setting register bit 16.14 = 1. 3.8.4.1 link failure link failure occurs if the link integrity test is enabled and link pulses or packets stop being received. if this condition occurs, the lxt971a returns to the auto-negotiation phase if auto- negotiation is enabled. if the link integrity te st function is disabled by setting register bit 16.14 = 1 in the configuration register, the lxt971a transmits packets, regardless of link status. 3.8.5 10base-t sqe (heartbeat) by default, the signal quality error (sqe) or h eartbeat function is disabled on the lxt971a. to enable this function, set register bit 16.9 = 1. when this function is enabled, the lxt971a asserts its col output for 5-15 bt after each packet. see figure 35 on page 67 for sqe timing parameters. 3.8.6 10base-t jabber if a transmission exceeds the jabber timer, the lxt971a disables the transmit and loopback functions. see figure 34 on page 67 for jabber timing parameters. the lxt971a automatically exits jabber mode after the unjabber time has expired. this function can be disabled by setting register bit 16.10 = 1. 3.8.7 10base-t polarity correction the lxt971a automatically detects and correct s for the condition where the receive signal (tpfip/n) is inverted. reversed pol arity is detected if eight inverted link pulses, or four inverted end-of-frame (eof) markers, are received consecuti vely. if link pulses or data are not received by the maximum receive time-out peri od (96-128 ms), the polarity st ate is reset to a non-inverted state. 3.9 monitoring operations 3.9.1 monitoring auto-negotiation auto-negotiation can be monitored as follows: ? register bit 17.7 is set to 1 once the auto-negotiation process is completed. ? register bits 1.2 and 17.10 are set to 1 once the link is established.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 45 document #: 249414 revision #: 002 rev. date: august 7, 2002 ? register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). 3.9.1.1 monitoring next page exchange the lxt971a offers an alternate next page mode to simplify the next page exchange process. normally, register bit 6.1 (page received) remains set until read. when alternate next page mode is enabled register bit 6.1 is au tomatically cleared whenever a new negotiation process takes place. this prevents the user from reading an old value in 6.1 and assuming that registers 5 and 8 (partner ability) contain valid information. add itionally, the lxt971a uses register bit 6.5 to indicate when the current received pa ge is the base page. this inform ation is useful for recognizing when next pages must be resent due to a new nego tiation process starting. register bits 6.1 and 6.5 are cleared when read. 3.9.2 led functions the lxt971a incorporates three di rect led drivers. on power up all the drivers are asserted for approximately 1 second after reset de-asserts. each led driver can be programmed using the led configuration register (refer to table 56 on page 85 ) to indicate one of the following conditions: ? operating speed ? transmit activity ? receive activity ? collision condition ? link status ? duplex mode the led drivers can also be programmed to display various combined status conditions. for example, setting register bits 20.15:12 = 11 01 produces the following combination of link and activity indications: ? if link is down led is off. ? if link is up led is on. ? if link is up and activity is detect ed, the led blinks at the stretc h interval selected by register bits 20.3:2 and continues to blink as long as activity is present. the led driver pins also provid e initial configuration settings. the led pins are sensitive to polarity and automatically pull up or pull down to c onfigure for either open drain or open collector circuits (10 ma max current rating) as required by the hardware configuration. refer to the discussion of ?hardware configuration settings? on page 30 for details. 3.9.2.1 led pulse stretching the led configuration register also provides optional led pulse stretching to 30, 60, or 100 ms. the pulse stretch time is further extended if the ev ent occurs again during this pulse stretch period. when an event such as receiving a packet occurs it is edge detected and it starts the stretch timer. the led driver remains asserted until the stretch ti mer expires. if another event occurs before the stretch timer expires then the stretch timer is reset and the stretch time is extended.
lxt971a 3.3v dual-speed fast ethernet transceiver 46 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 when a long event (such as duplex status) occurs it is edge detected and it starts the stretch timer. when the stretch timer expires the edge detector is reset so that a long event causes another pulse to be generated from the edge detector which resets the stretch timer and causes the led driver to remain asserted. figure 21 shows how the stretch operation functions. 3.10 boundary scan (jtag1149.1) functions lxt971a includes a ieee 1149.1 boundary scan test po rt for board level test ing. all di gital input, output, and input/out put pins are accessible. the bsdl file is available by co ntacting your local sales office or by accessing the intel website (www.intel.com) . 3.10.1 boundary scan interface this interface consists of five pins (tms, tdi, tdo, trst , and tck). it includes a state machine, data register array, and instruction register. the tms and tdi pins are internally pulled up. tck is internally pulled down. tdo does not ha ve an internal pull-up or pull-down. 3.10.2 state machine the tap controller is a 16 state machine driv en by the tck and tms pins. upon reset the test_logic_reset state is entere d. the state machine is also reset when tms and tdi are high for five tck periods. 3.10.3 instruction register after the state machine resets, the idcode inst ruction is always invoked. the decode logic ensures the correct data flow to the data regi sters according to the current instruction. valid instructions ar e listed in table 13 . 3.10.4 boundary scan register (bsr) each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the paralle l output stage. there are four modes of operation as listed in table 12 . figure 21. led pulse stretching event led note: the direct drive led outputs in this diagram are shown as active low. stretch stretch stretch
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 47 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 12. bsr mode of operation mode description 1capture 2shift 3 update 4 system function table 13. supported jtag instructions name code description mode data register extest 1111 1111 1110 1000 external test test bsr idcode 1111 1111 1111 1110 id c ode inspection normal id reg sample 1111 1111 1111 1000 sample b oundary normal bsr highz 1111 1111 1 100 1111 force float normal bypass clamp 1111 1111 1110 1111 control bo undary to 1/0 test bypass bypass 1111 1111 1111 1111 bypass scan normal bypass table 14. device id register 31:28 27:12 11:8 7:1 0 version 2 part id (hex) jedec continuation characters jedec id 1 reserved xxxx 03cb 0000 111 1110 1 1. the jedec is is an 8-bit identifier. the msb is fo r parity and is ignored. intel?s jedec id is fe (1111 1110), which becomes 111 1110. 2. see the lxt971a/972a specification update (docum ent number 249354) for the current version of the jedec continuation characters.
lxt971a 3.3v dual-speed fast ethernet transceiver 48 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 4.0 application information 4.1 magnetics information the lxt971a requires a 1: 1 ratio for both the receive and tran smit transformers. the transformer isolation voltage should be rated at 2 kv to prot ect the circuitry from static voltages across the connectors and cables. refer to table 15 for transformer requirements. a cross-reference list of magnetic manufacturer s and part numbers is available in magnetic manufacturers for networking product applicatio ns (document number 248991) and is found on the intel web site (www.intel.com). before committing to a specific component, contact the manufacturer for current product specifications and validate th e magnetics for the specific application. 4.2 typical twisted-pair interface table 16 provides a comparison of th e rj-45 connections for nic and switch applications in a typical twisted-pair interface setting. figure 22 on page 49 shows a typical twisted-pair interf ace with the rj-45 connections crossed over for a switch configuration. figure 23 on page 50 provides a typical twisted-pair interface with the rj-45 connections confi gured for a nic application. table 15. magnetics requirements parameter min nom max units test condition rx turns ratio ? 1 : 1 ? ? ? tx turns ratio ? 1 : 1 ? ? ? insertion loss 0.0 0.6 1.1 db ? primary inductance 350 ? ? h? transformer isolation ? 1.5 ? kv ? differential to common mode rejection 40 ? ? db .1 to 60 mhz 35 ? ? db 60 to 100 mhz return loss -16 ? ? db 30 mhz -10 ? ? db 80 mhz table 16. i/o pin comparison of nic and switch rj-45 setups symbol rj-45 switch nic tpip 1 3 tpin 2 6 tpop 3 1 tpon 6 2
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 49 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 22. typical twisted-pair interface - switch tpfip tpfin rj-45 * = 0.001 p f / 2.0 kv to twisted-pair network 3 6 1 2 1:1 lxt971a 50 : 50 : 50 : 50 : 50 : 50 : 4 5 8 7 1:1 1 tpfop tpfon vcca gnd 0.1 p f .01 p f 2 270 pf 5% 270 pf 5% 0.01 p f 50 : 50 : ** 3 sd/tp 4 0.1 p f 1. center-tap current may be supplied from 3.3 v vcca as shown. additional power savings may be realized by supplying the center-tap from a 2.5 v current source. a separate ferrite bead (rated at 50 ma) should be us ed to supply center-tap current. 2. the 100 : transmit load termination resistor typically required is integrated in the lxt971a. 3. magnetics without a receive pair center-tap do not require a 2 kv termination. 4. rj-45 connections shown are for a standard switch application. for a standard nic rj-45 setup, see figure 23 on page 50 .
lxt971a 3.3v dual-speed fast ethernet transceiver 50 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 23. typical twisted-pair interface - nic tpfip tpfin * = 0.001 f / 2.0 kv to twisted-pair network 1:1 lxt971a 1:1 1 tpfop tpfon vcca gnd 0.1 f .01 f 2 270 pf 5% 270 pf 5% 0.01 f 50 ? 1% 50 ? 1% ** 3 sd/tp 6 3 8 7 5 4 1 2 50 ? 50 ? 50 ? rj-45 50 ? 50 ? 50 ? 4 0.1 f 1. center-tap current may be supplied from 3.3 v v cca as shown. additional power savings may be realized by supplying the center-tap from a 2. 5 v current source. a separate ferrite bead (rated at 50 ma) should be used to supply center-tap current. 2. the 100 ? transmit load termination resistor typica lly required is integrated in the lxt971a. 3. magnetics without a receive pair cent er-tap do not require a 2 kv termination. 4. rj-45 connections shown for standard nic. tx/rx crossover may be required for repeater and switch applications.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 51 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 24. typical mii interface mac tx_en tx_er txd<3:0> tx_clk rx_dv rx_er rxd<3:0> crs col rx_clk lxt971a x f m r rj-45
lxt971a 3.3v dual-speed fast ethernet transceiver 52 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 4.3 the fiber interface the fiber interface consists of an lvpecl transmit and receive pa ir to an external fiber-optic transceiver. both 3.3 v fiber-optic transceivers a nd 5 v fiber-optic transcei vers can be used with the lxt971a. the following should occur in 3.3 v fibe r transceiver applications as shown in figure 25 : ? the transmit pair should be dc-coupled with the 50 ? /16 ? pull-up combination ? the receive pair should be dc-coupled with an emitter current path for the fiber transceiver ? the signal detect pin should be dc-coupled with an emitter current path for the fiber transceiver refer to the fiber transceiver manufacturer?s recommendations for te rmination circuitry. figure 25 shows a typical example of an lxt971 a-to-3.3 v fiber transceiver interface. the following occurs in 5 v fiber tr ansceiver applications as shown in figure 26 : ? the transmit pair should be ac-coupled and re-biased to 5 v pecl input levels ? the receive pair should be ac-coupled with an emitter current path for the fiber transceiver and re-biased to 3.3 v lvpecl input levels. the signal detect pin on a 5 v fibe r transceiver interface s hould use the logic translator circuitry as shown in figure 27 . refer to the fiber transceiver manufact urer?s recommendations for termination circuitry. figure 26 shows a typical example of an lxt971 a-to-5 v fiber transceiver interface, while figure 27 shows the interface circuitr y for the logic translator.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 53 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 25. typical lxt971a-to-3.3 v fiber transceiver interface circuitry lxt971a tpfin tpfip tpfop tpfon to fiber network fiber txcvr td - td + rd - rd + sd sd/tp +3.3v +3.3v +3.3v 0.01 f ? 0.1 f 16? 50? 50? 130? 82? 1 +3.3v 0.01 f ? 0.1 f 82? 82? 130? 130 ? 1. refer to the transceiver manufacturer?s recommendations for te rmination circuitry.
lxt971a 3.3v dual-speed fast ethernet transceiver 54 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 26. typical lxt971a-to-5 v fi ber transceiver interface circuitry lxt971a tpfin tpfip tpfop tpfon to fiber network fiber txcvr td - td + rd - rd + sd sd/tp +3.3v +3.3v 0.01 f 0.01 f 0.01 f ? 0.1 f 0.01 f 0.01 f on semiconductor mc100lvel92 pecl-to-lvpecl logic translator 2 16? 50? 50? 270? 270? 1 +5v 3.1 k ? 3.1 k ? 1.1 k ?1.1 k ? 0.01 f ? 0.1 f +3.3v 0.01 f ? 0.1 f 154? 154? 102? 102? 1. refer to the transceiver manufacturer?s recommendations for termination circuitry. 2. see figure 27 for recommended logic translator interface circuitry.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 55 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 27. on semiconductor tr iple pecl-to-lvpecl translator 5v vcc d0 __ d0 vbb pecl d1 __ d1 vbb pecl d2 __ d2 gnd vcc q0 __ q0 lvcc q1 __ q1 lvcc q2 __ q2 vcc 0.01 f 0.01 f 3.3v lvpecl output signal (lxt971a) pecl input signal (5v fiber txcvr) 3.3v 130 ? 82 ? 5v 130 ? 82 ? on semiconductor mc100lvel92 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.01 f 3.3v 130 ? 82 ?
lxt971a 3.3v dual-speed fast ethernet transceiver 56 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 5.0 test specifications note: table 17 through table 40 and figure 28 through figure 41 represent the performance specifications of the lxt 971a. these specifications are guaran teed by test except where noted ?by design.? minimum and maximum values listed in table 19 through table 40 apply over the recommended operating conditions specified in table 18 . 5.1 electrical parameters table 17. absolute maximum ratings parameter sym min max units supply voltage v cc -0.3 4.0 v operating temperature lxt971a_c (commercial) t opa -15 +85 oc lxt971a_e (extended) t opa -55 +100 oc storage temperature t st -65 +150 oc caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 18. operating conditions parameter sym min typ 1 max units recommended operating temperature lxt971a_c (commercial) t opa 0?70oc lxt971a_e (extended) t opa -40 ? 85 oc recommended supply voltage 2 analog & digital vcca, vccd 3.14 3.3 3.45 v i/o vccio 2.35 ? 3.45 v v cc current 100base-tx i cc ?92110ma 10base-t i cc ?6682ma 100base-fx i cc ?7295ma sleep mode i cc ?4045ma hard power down i cc ?? 1ma soft power down icc ? 51 ? ma auto-negotiation i cc ?90110ma 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. voltages with respect to ground unless otherwise specified.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 57 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 19. digital i/o characteristics 2 parameter symbol min typ 1 max units test conditions input low voltage v il ? ? 0.8 v ? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a 0.0 < v i < v cc output low voltage v ol ? ? 0.4 v i ol = 4 ma output high voltage v oh 2.4 ? ? v i oh = -4 ma 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. applies to all pins except mii, led, xi/xo, and sd/tp pins. refer to table 20 for mii i/o c haracteristics, table 21 for xi/xo and table 22 for led characteristics. table 20. digital i/o characteristics - mii pins parameter symbol min typ 1 max units test conditions input low voltage v il ? ? 0.8 v ? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a 0.0 < v i < vccio output low voltage v ol ? ? 0.4 v i ol = 4 ma output high voltage v oh 2.2 ? ? v i oh = -4 ma, vccio = 3.3v v oh 2.0 ? ? v i oh = -4 ma, vccio = 2.5v driver output resistance (line driver output enabled) r o 2 ? 100 ? w vccio = 2.5v r o 2 ? 100 ? w vccio = 3.3v 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. table 21. i/o characteristics - refclk/xi and xo pins parameter symbol min typ 1 max units test conditions input low voltage v il ? ? 0.8 v ? input high voltage v ih 2.0 ? ? v ? input clock frequency tolerance 2 ? f ?? 100 ppm ? input clock duty cycle 2 tdc 35 ? 65 % ? input capacitance c in ?3.0 ? pf ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing.
lxt971a 3.3v dual-speed fast ethernet transceiver 58 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 22. i/o characteristics - led/cfg pins parameter symbol min typ max units test conditions input low voltage v il ? ? 0.8 v ? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a0 < v i < vccio output low voltage v ol ? ? 0.4 v i ol = 10 ma output high voltage v oh 2.0 ? ? v i oh = -10 ma table 23. i/o characteristics ? sd/tp pin parameter sym min typ 1 max units test conditions reset and power-up states ? fx/tp mode configuration fiber mode (register bit 16.0 = 1) v fx 600 1600-2400 ? mv ? twisted-pair mode (register bit 16.0 = 0) v tp ? gnd 500 mv ? 100base-fx mode normal operation ? sd input from fiber transceiver input low voltage v il 1.49 1.6 1.83 v vccd = 3.3 v input high voltage v ih 2.14 2.4 2.42 v vccd = 3.3 v 1. typical values are for design aid only; not guaranteed and not subject to production testing. table 24. 100base-tx transceiver characteristics parameter symbol min typ 1 max units test conditions peak differential output voltage v p 0.95 ? 1.05 v note 2 signal amplitude symmetry vss 98 ? 102 % note 2 signal rise/fall time t rf 3.0 ? 5.0 ns note 2 rise/fall time symmetry t rfs ? ? 0.5 ns note 2 duty cycle distortion d cd 35 50 65 % offset from 16 ns pulse width at 50% of pulse peak overshoot/undershoot v os ?? 5 % ? jitter (measured differentially) ? ? ? 1.4 ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 ? (+/-1%) resistor.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 59 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 25. 100base-fx transceiver characteristics parameter symbol min typ 1 max units test conditions transmitter peak differential output voltage (single ended) v op 0.6 ? 1.5 v ? signal rise/fall time t rf ? ? 1.9 ns 10 90% 2.0 pf load jitter (measured differentially) ? ? ? 1.3 ns ? receiver peak differential input voltage v ip 0.55 ? 1.5 v ? common mode input range v cmir ??v cc - 0.7 v ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. table 26. 10base-t transceiver characteristics parameter symbol min typ max units test conditions transmitter peak differential output voltage v op 2.2 2.5 2.8 v with transformer, line replaced by 100 ? resistor transition timing jitter added by the mau and pls sections ?0211ns after line model specified by ieee 802.3 for 10base-t mau receiver receive input impedance z in ? ? 22 k ? ? differential squelch threshold v ds 300 420 585 mv ? table 27. 10base-t link integrity timing characteristics parameter symbol min typ max units test conditions time link loss receive t ll 50 ? 150 ms ? link pulse t lp 2 ? 7 link pulses ? link min receive timer t lr m in 2?7 ms ? link max receive timer t lr m ax 50 ? 150 ms ? link transmit period tlt 8 ? 24 ms ? link pulse width tlpw 60 ? 150 ns ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing.
lxt971a 3.3v dual-speed fast ethernet transceiver 60 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 28. lxt971a thermal characteristics parameter lxt971alc lxt971ale lxt971abe package 1 0x 10 x1.4 64 ld lqfp 10 x 10 x 1.4 64 lqfp 7 x 7 x .96 64 bga-csp theta-ja 58 c/w 56 c/w 42 c/w theta-jc 27 c/w 25 c/w 20 c/w psi - jt 3.4 c/w 3.0 c/w ?
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 61 document #: 249414 revision #: 002 rev. date: august 7, 2002 5.2 timing diagrams figure 28. 100base-tx receive timing - 4b mode table 29. 100base-tx receive timing parameters - 4b mode parameter sym min typ 1 max units 2 test conditions rxd<3:0>, rx_dv, rx_er setup to rx_clk high t1 10 ? ? ns ? rxd<3:0>, rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? crs asserted to rxd<3:0>, rx_dv t3 3 ? 5 bt ? receive start of ?j? to crs asserted t4 12 ? 16 bt ? receive start of ?t? to crs de-asserted t5 10 ? 17 bt ? receive start of ?j? to col asserted t6 16 ? 22 bt ? receive start of ?t? to col de-asserted t7 17 ? 20 bt ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and fr om the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. t4 t5 t3 t6 t7 0ns 250ns crs rx_dv rxd<3:0> rx_clk col t1 t2 tpfi
lxt971a 3.3v dual-speed fast ethernet transceiver 62 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 29. 100base-tx transmit timing - 4b mode table 30. 100base-tx transmit timing parameters - 4b mode parameter symbol min typ 1 max units 2 test conditions txd<3:0>, tx_en, tx_er setup to tx_clk high t1 12 ? ? ns ? txd<3:0>, tx_en, tx_er hold from tx_clk high t2 0 ? ? ns ? tx_en sampled to crs asserted t3 20 ? 24 bt ? tx_en sampled to crs de-asserted t4 24 ? 28 bt ? tx_en sampled to tpfo out (tx latency) t5 5.3 ? 5.7 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and fr om the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd<3:0> tpfo crs
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 63 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 30. 100base-fx receive timing table 31. 100base-fx receive timing parameters parameter sym min typ 1 max units 2 test conditions rxd<3:0>, rx_dv, rx_er setup to rx_clk high t1 10 ? ? ns ? rxd<3:0>, rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? crs asserted to rxd<3:0>, rx_dv t3 3 ? 5 bt ? receive start of ?j? to crs asserted t4 12 ? 16 bt ? receive start of ?t? to crs de-asserted t5 16 ? 22 bt ? receive start of ?j? to col asserted t6 10 ? 15 bt ? receive start of ?t? to col de-asserted t7 14 ? 18 bt ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and fr om the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. t4 t5 t3 t6 t7 0ns 250ns crs rx_dv rxd<3:0> rx_clk col t1 t2 tpfi
lxt971a 3.3v dual-speed fast ethernet transceiver 64 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 31. 100base-fx transmit timing table 32. 100base-fx transmit timing parameters parameter symbol min typ 1 max units 2 test conditions txd<3:0>, tx_en, tx_er setup to tx_clk high t1 12 ? ? ns ? txd<3:0>, tx_en, tx_er hold from tx_clk high t2 0 ? ? ns ? tx_en sampled to crs asserted t3 17 ? 20 bt ? tx_en sampled to crs de-asserted t4 22 ? 24 bt ? tx_en sampled to tpfo out (tx latency) t5 5 ? 5.3 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and fr om the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd<3:0> tpfo crs
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 65 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 32. 10base-t receive timing table 33. 10base-t receive timing parameters parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t1 10 ? ? ns ? rxd, rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? tpfip/n in to rxd out (rx latency) t3 4.2 ? 6.6 bt ? crs asserted to rxd, rx_dv, rx_er asserted t4 5 ? 32 bt ? rxd, rx_dv, rx_er de-asserted to crs de-asserted t5 0.3 ? 0.5 bt ? tpfi in to crs asserted t6 2 ? 28 bt ? tpfi quiet to crs de-asserted t7 6 ? 10 bt ? tpfi in to col asserted t8 1 ? 31 bt ? tpfi quiet to col de-asserted t9 5 ? 10 bt ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and fr om the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. rx_clk rxd, rx_dv, rx_er crs tpfi t 3 t 4 t 2 t 6 t 1 t 7 t 5 col t 8 t 9
lxt971a 3.3v dual-speed fast ethernet transceiver 66 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 33. 10base-t transmit timing table 34. 10base-t transmit timing parameters parameter symbol min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t1 10 ? ? ns ? txd, tx_en, tx_er hold from tx_clk high t2 0 ? ? ns ? tx_en sampled to crs asserted t3 ? 2 ? bt ? tx_en sampled to crs de-asserted t4 ? 1 ? bt ? tx_en sampled to tpfo out (tx latency) t5 ? 72.5 ? bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and fr om the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. tx_clk txd, tx_en, tx_er crs tpfo t 1 t 3 t 4 t 5 t 2
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 67 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 34. 10base-t jabber and unjabber timing table 35. 10base-t jabber and unjabber timing parameters parameter symbol min typ 1 max units test conditions maximum transmit time t1 20 ? 150 ms ? unjab time t2 250 ? 750 ms ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. figure 35. 10base-t sqe (heartbeat) timing table 36. 10base-t sqe timing parameters parameter symbol min typ 1 max units test conditions col (sqe) delay after tx_en off t1 0.65 ? 1.6 us ? col (sqe) pulse duration t2 0.5 ? 1.5 us ? 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. txd col t 1 t 2 tx_en tx_clk tx_en t 1 t 2 col
lxt971a 3.3v dual-speed fast ethernet transceiver 68 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 36. auto-negotiation and fast link pulse timing figure 37. fast link pulse timing table 37. auto-negotiation and fast link pulse timing parameters parameter symbol min typ 1 max units test conditions clock/data pulse width t1 ? 100 ? ns ? clock pulse to data pulse t2 55.5 ? 63.8 s? clock pulse to clock pulse t3 123 ? 127 s? flp burst width t4 ? 2 ? ms ? flp burst to flp burst t5 8 12 24 ms ? clock/data pulses per burst ? 17 ? 33 ea ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. tpfop t1 t1 t2 t3 clock pulse data pulse clock pulse tpfop t4 t5 flp burst flp burst
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 69 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 38. mdio input timing figure 39. mdio output timing table 38. mdio timing parameters parameter symbol min typ 1 max units test conditions mdio setup before mdc, sourced by sta t1 10 ? ? ns ? mdio hold after mdc, sourced by sta t2 5 ? ? ns ? mdc to mdio output delay, source by phy t3 ? ? 150 ns ? mdc period t4 125 ? ? ns mdc = 8 mhz 1. typical values are at 25 c and are for design ai d only; not guaranteed and not subject to production testing. t1 mdc mdio t2 t3 mdc mdio t4
lxt971a 3.3v dual-speed fast ethernet transceiver 70 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 40. po wer-up timing table 39. power-up timing parameters parameter symbol min typ 1 max units test conditions voltage threshold v1 ? 2.9 ? v ? power up delay 2 t1 ? ? 300 s? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. power-up delay is specified as a maximum value because it refers to the phy guaranteed performance - the phy comes out of reset after a delay of no more than 300 s. system designers s hould consider this as a minimum value - after threshold v1 is reached, the mac should delay no less than 300 s before accessing the mdio port. figure 41. reset pulse width and recovery timing table 40. reset pulse width and recove ry timing parameters parameter symbol min typ 1 max units test conditions reset pulse width t1 10 ? ? ns ? reset recovery delay 2 t2 ? 300 s? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. reset recovery delay is specified as a maximum value because it refers to the phy guaranteed performance - the phy comes out of reset after a delay of no more than 300 s. system designers should consider this as a minimum value - after de-asserting reset*, the mac should delay no less than 300 s before accessing the mdio port. t1 vcc mdio,etc v1 t2 reset mdio,etc t1
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 71 document #: 249414 revision #: 002 rev. date: august 7, 2002 6.0 register definitions the lxt971a register se t includes multiple 16-bit registers. table 41 presents a complete register listing. table 42 is a complete memory map of all registers and tables 43 through 58 provide individual register definitions. base registers (0 through 8) are defined in accordance with the ?reconciliation sublayer and media independent interface? an d ?physical layer link signaling for 10/100 mbps auto- negotiation? sections of the ieee 802.3 standard. additional registers are defined in accordance with the ieee 802.3 standard for adding unique chip functions. table 41. register set address register name bit assignments 0 control register refer to table 43 on page 74 1 status register #1 refer to table 44 on page 75 2 phy identification register 1 refer to table 45 on page 76 3 phy identification register 2 refer to table 46 on page 76 4 auto-negotiation advertisement register refer to table 47 on page 77 5 auto-negotiation link partner base page ability register refer to table 48 on page 78 6 auto-negotiation expansion register refer to table 49 on page 79 7 auto-negotiation next page transmit register refer to table 50 on page 79 8 auto-negotiation link partner received next page register refer to table 51 on page 80 9 1000base-t/100base-t2 control register not implemented 10 1000base-t/100base-t2 status register not implemented 15 extended status register not implemented 16 port configuration register refer to table 52 on page 81 17 status register #2 refer to table 53 on page 82 18 interrupt enable register refer to table 54 on page 83 19 interrupt status register refer to table 55 on page 84 20 led configuration register refer to table 56 on page 85 21-25 reserved ? 26 digital config register refer to table 57 on page 86 27-29 reserved ? 30 transmit control register refer to table 58 on page 87
lxt971a 3.3v dual-speed fast ethernet transceiver 72 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 42. register bit map reg title bit fields addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control register control reset loopbac k speed select a/n enable power down isolate re-start a/n duplex mode col test speed select reserved 0 status register status 100base- t4 100base- x full duplex 100base- x half duplex 10mbps full duplex 10mbps half duplex 100base- t2 full duplex 100base- t2 half duplex extended status reserved mf preamble suppress a/n complete remote fault a/n ability link status jabber detect extended capabilit y 1 phy id registers phy id 1 15141312 11 109876543210 2 phy id2 phy id no mfr model no mfr rev no 3 auto-negotiation advertisement register a/n advertise next page reserved remote fault reserved asymm pause pause 100base- t4 100base- tx full duplex 100base- tx 10base-t full duplex 10base-t ieee selector field 4 auto-negotiation link partner base page ability register a/n link ability next page ack remote fault reserved asymm pause pause 100base- t4 100base- tx full duplex 100base- tx 10base-t full duplex 10base-t ieee selector field 5 auto-negotiation expansion register a/n expansion reserved base page parallel detect fault link partner next page able next page able page received link partner a/n able 6 auto-negotiation next page transmit register a/n next page txmit next page reserved message page ack 2 toggle message / unformatted code field 7 auto-negotiation link partner next page receive register
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 73 document #: 249414 revision #: 002 rev. date: august 7, 2002 a/n link next page next page ack message page ack 2 toggle message / unformatted code field 8 configuration register port config reserved force link pass txmit disable bypass scrambler (100tx) reserved jabber (10t) sqe (10t) tp loopbac k (10t) crs select (10t) sleep mode pre_en sleep timer fault code enable alternate next page fiber select 16 status register #2 status register #2 reserved 10/100 mode transmit status receive status collision status link duplex mode auto- neg auto- neg complete reserved polarity pause error reserved reserved 17 interrupt enable register interrupt enable reserved reserved auto- neg mask speed mask duplex mask link mask reserved reserved interrupt enable test interrupt 18 interrupt status register interrupt status reserved reserved auto- neg done speed change duplex change link change reserved md interrupt reserved reserved 19 led configuration register led config led1 led2 led3 led freq pulse stretch reserved 20 digital config register (address 26) digital config reserved increased mii drive strength reserved show symbol error reserved 26 transmit control register trans. control reserved transmit low pwr port rise time control reserved 30 table 42. register bit map (continued) reg title bit fields addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
lxt971a 3.3v dual-speed fast ethernet transceiver 74 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 43. control register (address 0) bit name description type 1 default 0.15 reset 1 = phy reset 0 = normal operation r/w sc 0 0.14 loopback 1 = enable loopback mode 0 = disable loopback mode r/w 0 0.13 speed selection 0.6 0.13 speed selected r/w note 2 1 1 0 0 1 0 1 0 reserved 1000 mbps (not supported) 100 mbps 10 mbps 0.12 auto-negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process r/w note 2 0.11 power-down 1 = power-down 0 = normal operation r/w 0 0.10 isolate 1 = electrically isolate phy from mii 0 = normal operation r/w 0 0.9 restart auto-negotiation 1 = restart auto-negotiation process 0 = normal operation r/w sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex r/w note 2 0.7 collision test 1 = enable col signal test 0 = disable col signal test r/w 0 0.6 speed selection 0.6 0.13 speed selected r/w 0 1 1 0 0 1 0 1 0 reserved 1000 mbps (not supported) 100 mbps 10 mbps 0.5:0 reserved write as 0, ignore on read r/w 00000 1. r/w = read/write ro = read only sc = self clearing 2. default value of register bits 0.12, 0.13 and 0.8 are determined by the led/cfg n pins (refer to table 9 on page 30 ).
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 75 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 44. mii status register #1 (address 1) bit name description type 1 default 1.15 100base-t4 not supported 1 = phy able to perform 100base-t4 0 = phy not able to perform 100base-t4 ro 0 1.14 100base-x full-duplex 1 = phy able to perform full-duplex 100base-x 0 = phy not able to perform full-duplex 100base-x ro 1 1.13 100base-x half-duplex 1 = phy able to perform half-duplex 100base-x 0 = phy not able to perform half-duplex 100base-x ro 1 1.12 10 mbps full-duplex 1 = phy able to operate at 10 mbps in full-duplex mode 0 = phy not able to operate at 10 mbps full-duplex mode ro 1 1.11 10 mbps half-duplex 1 = phy able to operate at 10 mbps in half-duplex mode 0 = phy not able to operate at 10 mbps in half- duplex ro 1 1.10 100base-t2 full- duplex not supported 1 = phy able to perform full-duplex 100base-t2 0 = phy not able to perform full-duplex 100base-t2 ro 0 1.9 100base-t2 half- duplex not supported 1 = phy able to perform half-duplex 100base-t2 0 = phy not able to perform half-duplex 100base- t2 ro 0 1.8 extended status 1 = extended status information in register 15 0 = no extended status information in register 15 ro 0 1.7 reserved 1 = ignore when read ro 0 1.6 mf preamble suppression 1 = phy accepts management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed ro 0 1.5 auto-negotiation complete 1 = auto-negotiation complete 0 = auto-negotiation not complete ro 0 1.4 remote fault 1 = remote fault condition detected 0 = no remote fault condition detected ro/lh 0 1.3 auto-negotiation ability 1 = phy is able to perform auto-negotiation 0 = phy is not able to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber condition detected 0 = jabber condition not detected ro/lh 0 1.0 extended capability 1 = extended register capabilities 0 = basic regist er capabilities ro 1 1. ro = read only ll = latching low lh = latching high
lxt971a 3.3v dual-speed fast ethernet transceiver 76 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 45. phy identification register 1 (address 2) bit name description type 1 default 2.15:0 phy id number the phy identifier composed of bits 3 through 18 of the oui. ro 0013 hex 1. ro = read only table 46. phy identification register 2 (address 3) bit name description type 1 default 3.15:10 phy id number the phy identifier composed of bits 19 through 24 of the oui. ro 011110 3.9:4 manufacturer?s model number 6 bits containing manufacturer?s part number. ro 001110 3.3:0 manufacturer?s revision number 4 bits containing manufacturer?s revision number. ro xxxx (see the lxt971a/972a specification update) 1. ro = read only figure 42. phy iden tifier bit mapping 0 00000 0 0 00 00010011011110 00111000 abc rs x 15 0 15 10 9 4 3 0 00 the intel oui is 00207b hex phy id register #1 (address 2) = 0013 phy id register #2 (address 3) manufacturer?s model number revision number organizationally un ique identifier 00 20 7b 5030
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 77 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 47. auto-negotiation advertisement register (address 4) bit name description type 1 default 4.15 next page 1 = port has ability to send multiple pages. 0 = port has no ability to send multiple pages. r/w 0 4.14 reserved ignore. ro 0 4.13 remote fault 1 = remote fault. 0 = no remote fault. r/w 0 4.12 reserved ignore. r/w 0 4.11 asymmetric pause pause operation defined in clause 40 and 27. r/w 0 4.10 pause 1 = pause operation enabled for full-duplex links. 0 = pause operation disabled. r/w note 2 4.9 100base-t4 1 = 100base-t4 capability is available. 0 = 100base-t4 capability is not available. (the lxt971a does not support 100base-t4 but allows this bit to be set to advertise in the auto- negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver could be switched in if this capability is desired.) r/w 0 4.8 100base-tx full-duplex 1 = port is 100base-tx full-duplex capable. 0 = port is not 100base-tx full-duplex capable. r/w note 3 4.7 100base-tx 1 = port is 100base-tx capable. 0 = port is not 100base-tx capable. r/w note 3 4.6 10base-t full-duplex 1 = port is 10base-t full-duplex capable. 0 = port is not 10base-t full-duplex capable. r/w note 3 4.5 10base-t 1 = port is 10base-t capable. 0 = port is not 10base-t capable. r/w note 3 4.4:0 selector field, s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto- negotiation development. unspecified or reserved co mbinations should not be transmitted. r/w 00001 1. r/w = read/write ro = read only 2. the default setting of register bit 4.10 (pause) is determined by pin 33/h8 at reset. 3. default values of register bits 4.5, 4.6, 4.7, and 4.8 are determined by led/cfg n pins at reset. refer to table 9 for details.
lxt971a 3.3v dual-speed fast ethernet transceiver 78 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 48. auto-negotiation link partner base page ability re gister (address 5) bit name description type 1 default 5.15 next page 1 = link partner has ability to send multiple pages. 0 = link partner has no ability to send multiple pages. ro n/a 5.14 acknowledge 1 = link partner has received link code word from lxt971a. 0 = link partner has not received link code word from the lxt971a. ro n/a 5.13 remote fault 1 = remote fault. 0 = no remote fault. ro n/a 5.12 reserved ignore. ro n/a 5.11 asymmetric pause pause operation defined in clause 40 and 27. 1 = link partner is pause capable. 0 = link partner is not pause capable. ro n/a 5.10 pause 1 = link partner is pause capable. 0 = link partner is not pause capable. ro n/a 5.9 100base-t4 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. ro n/a 5.8 100base-tx full-duplex 1 = link partner is 100base-tx full-duplex capable. 0 = link partner is not 100base-tx full-duplex capable. ro n/a 5.7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. ro n/a 5.6 10base-t full-duplex 1 = link partner is 10base-t full-duplex capable. 0 = link partner is not 10base-t full-duplex capable. ro n/a 5.5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. ro n/a 5.4:0 selector field s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-n egotiation development. unspecified or reserved combinations shall not be transmitted. ro n/a 1. ro = read only
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 79 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 49. auto-negotiation expansion (address 6) bit name description type 1 default 6.15:6 reserved ignore on read. ro 0 6.5 base page this bit indicates the status of the auto-negotiation variable base page. it flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links. this bit is only used if register bit 16.1 (alternate np feature) is set. 1 = base page = true 0 = base page = false ro/ lh 0 6.4 parallel detection fault 1 = parallel detection fault has occurred. 0 = parallel detection fault has not occurred. ro/ lh 0 6.3 link partner next page able 1 = link partner is next page able. 0 = link partner is not next page able. ro 0 6.2 next page able 1 = local device is next page able. 0 = local device is not next page able. ro 1 6.1 page received 1 = indicates that a new page has been received and the received code word has been loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of ieee 802.3. this bit is cleared on read. if register bit 16.1 is set, the page received bit is also cleared when mr_page_rx = false or transmit_disable = true. ro lh 0 6.0 link partner a/n able 1 = link partner is auto-negotiation able. 0 = link partner is not auto-negotiation able. ro 0 1. ro = read only lh = latching high table 50. auto-negotiation next page transmit register (address 7) bit name description type 1 default 7.15 next page (np) 1 = additional next pages follow 0 = last page r/w 0 7.14 reserved write as 0, ignore on read ro 0 7.13 message page (mp) 1 = message page 0 = unformatted page r/w 1 7.12 acknowledge 2 (ack2) 1 = complies with message 0 = cannot comply with message r/w 0 7.11 toggle (t) 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one r/w 0 7.10:0 message/unformatted code field r/w 00000000 001 1. ro = read only. r/w = read/write
lxt971a 3.3v dual-speed fast ethernet transceiver 80 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 51. auto-negotiation link partner next page receive register (address 8) bit name description type 1 default 8.15 next page (np) 1 = link partner has additional next pages to send 0 = link partner has no additional next pages to send ro 0 8.14 acknowledge (ack) 1 = link partner has received link code word from lxt971a 0 = link partner has not received link code word from lxt971a ro 0 8.13 message page (mp) 1 = page sent by the link partner is a message page 0 = page sent by the link partner is an unformatted page ro 0 8.12 acknowledge 2 (ack2) 1 = link partner complies with the message 0 = link partner cannot comply with the message ro 0 8.11 toggle (t) 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one ro 0 8.10:0 message/unformatted code field user definable ro 0 1. ro = read only.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 81 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 52. configuration register (address 16, hex 10) bit name description type 1 default 16.15 reserved write as zero, ignore on read. r/w 0 16.14 force link pass 1 = force link pass 0 = normal operation r/w 0 16.13 transmit disable 1 = disable twisted pair transmitter 0 = normal operation r/w 0 16.12 bypass scrambler (100base-tx) 1 = bypass scrambler and descrambler 0 = normal operation r/w 0 16.11 reserved ignore r/w 0 16.10 jabber (10base-t) 1 = disable jabber correction 0 = normal operation r/w 0 16.9 sqe (10base-t) 1 = enable heart beat 0 = disable heart beat r/w 0 16.8 tp loopback (10base-t) 1 = disable tp loopback during half-duplex operation 0 = normal operation r/w 0 16.7 crs select (10base-t) 1 = crs deassert extends to rx_dv deassert 0 = normal operation r/w 1 16.6 sleep mode 1 = enable sleep mode 0 = disable sleep mode r/w note 2 16.5 pre_en preamble enable. 0 = set rx_dv high coincident with sfd. 1 = set rx_dv high and rxd = preamble when crs is asserted. r/w 0 16.4:3 sleep timer 00 = 3.04 seconds 01 = 2.00 seconds 10 = 1.04 seconds r/w 00 16.2 fault code enable 1 = enable fefi transmission 0 = disable fefi transmission r/w 1 16.1 alternate np feature 1 = enable alternate auto negotiate next page feature. 0 = disable alternate auto negotiate next page feature r/w 0 16.0 fiber select 1 = select fiber mode. 0 = select tp mode. r/w note 3 1. r/w = read /write lhr = latches high on reset 2. the default value of register bit 16.6 is determined by the state of the sleep pin 32/h7. 3. the default value of register bit 16. 0 is determined by pin 26/g2 (sd/tp ).
lxt971a 3.3v dual-speed fast ethernet transceiver 82 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 53. status register #2 (address 17) bit name description type 1 default 17.15 reserved always 0. ro 0 17.14 10/100 mode 1 = lxt971a is operating in 100base-tx mode. 0 = lxt971a is not operating 100base-tx mode. ro 0 17.13 transmit status 1 = lxt971a is transmitting a packet. 0 = lxt971a is not transmitting a packet. ro 0 17.12 receive status 1 = lxt971a is receiving a packet. 0 = lxt971a is not receiving a packet. ro 0 17.11 collision status 1 = collision is occurring. 0 = no collision. ro 0 17.10 link 1 = link is up. 0 = link is down. ro 0 17.9 duplex mode 1 = full-duplex. 0 = half-duplex. ro 0 17.8 auto-negotiation 1 = lxt971a is in auto-negotiation mode. 0 = lxt971a is in manual mode. ro 0 17.7 auto-negotiation complete 1 = auto-negotiation process completed. 0 = auto-negotiation process not completed. this bit is only valid when auto negotiate is enabled, and is equivalent to register bit 1.5. ro 0 17.6 reserved always 0. ro 0 17.5 polarity 1 = polarity is reversed. 0 = polarity is not reversed. ro 0 17.4 pause 1 = device pause capable. 0 = device not pause capable. ro 0 17:3 error 1 = error occurred (remote fault, x,y, z). 0 = no error occurred. ro 0 17:2 reserved always 0. ro 0 17:1 reserved always 0. ro 0 17.0 reserved always 0. ro 0 1. ro = read only. r/w = read/write
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 83 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 54. interrupt enable register (address 18) bit name description type 1 default 18.15:9 reserved write as 0; ignore on read. r/w n/a 18.8 reserved write as 0; ignore on read. r/w 0 18.7 anmsk mask for auto negotiate complete 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.6 speedmsk mask for speed interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.5 duplexmsk mask for duplex interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.4 linkmsk mask for link status interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.3 reserved write as 0, ignore on read. r/w 0 18.2 reserved write as 0, ignore on read. r/w 0 18.1 inten 1 = enable interrupts. 0 = disable interrupts. r/w 0 18.0 tint 1 = force interrupt on mdint . 0 = normal operation. r/w 0 1. r/w = read /write
lxt971a 3.3v dual-speed fast ethernet transceiver 84 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 table 55. interrupt status register (address 19, hex 13) bit name description type 1 default 19.15:9 reserved ignore ro n/a 19.8 reserved ignore ro 0 19.7 andone auto-negotiation status 1= auto-negotiation has completed. 0= auto-negotiation has not completed. ro/sc n/a 19.6 speedchg speed change status 1 = a speed change has occurred since last reading this register. 0 = a speed change has not occurred since last reading this register. ro/sc 0 19.5 duplexchg duplex change status 1 = a duplex change has occurred since last reading this register. 0 = a duplex change has not occurred since last reading this register. ro/sc 0 19.4 linkchg link status change status 1 = a link change has occurred since last reading this register. 0 = a link change has not occurred since last reading this register. ro/sc 0 19.3 reserved ignore. ro 0 19.2 mdint 1 = mii interrupt pending. 0 = no mii interrupt pending. ro 19.1 reserved ignore. ro n/a 19.0 reserved ignore ro 0 1. r/w = read/write, ro = read only, sc = self clearing.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 85 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 56. led configuration re gister (address 20, hex 14) bit name description type 1 default 20.15:12 led1 programming bits 0000 = display speed status (continuous, default) 0001 = display transmit status (stretched) 0010 = display receive status (stretched) 0011 = display collision status (stretched) 0100 = display link status (continuous) 0101 = display duplex status (continuous) 0110 = unused 0111 = display receive or transmit activity (stretched) 1000 = test mode- turn led on (continuous) 1001 = test mode- turn led off (continuous) 1010 = test mode- blink led fast (continuous) 1011 = test mode- blink led slow (continuous) 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0000 20.11:8 led2 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status 0011 = display collision status 0100 = display link status (default) 0101 = display duplex status 0110 = unused 0111 = display receive or transmit activity 1000 = test mode- turn led on 1001 = test mode- turn led off 1010 = test mode- blink led fast 1011 = test mode- blink led slow 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0100 1. r/w = read /write ro = read only lh = latching high 2. link status is the primary led driver. the le d is asserted (solid on) when the link is up. the secondary led driver (receive or activi ty) causes the led to change state (blink). 3. combined event led settings are not affected by puls e stretch register bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are relative approximations. not guaranteed or production tested.
lxt971a 3.3v dual-speed fast ethernet transceiver 86 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 20.7:4 led3 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status (default) 0011 = display collision status 0100 = display link status 0101 = display duplex status 0110 = unused 0111 = display receive or transmit activity 1000 = test mode- turn led on 1001 = test mode- turn led off 1010 = test mode- blink led fast 1011 = test mode- blink led slow 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0010 20.3:2 ledfreq 5 00 = stretch led events to 30 ms. 01 = stretch led events to 60 ms. 10 = stretch led events to 100 ms. 11 = reserved. r/w 00 20.1 pulse- stretch 0 = disable pulse stretching of all leds. 1 = enable pulse stretching of all leds. r/w 1 20.0 reserved ignore. r/w n/a table 57. digital config register (address 26) bit name description type 1 default 26.15:12 reserved reserved ro 0 26.11 mii drive strength 1 = increased mii drive strength 0 = normal mii drive strength r/w 0 26.10 reserved reserved ro 0 26.9 show symbol error 1 = map symbol error signal to rxer 0 = normal rxer r/w 0 26.8:0 reserved reserved ro 0 1. r/w = read /write, ro = read only, lh = latching high table 56. led configuration register (address 20, hex 14) (continued) bit name description type 1 default 1. r/w = read /write ro = read only lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity ) causes the led to change state (blink). 3. combined event led settings are not affected by puls e stretch register bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are relative approximations. not guaranteed or production tested.
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 87 document #: 249414 revision #: 002 rev. date: august 7, 2002 table 58. transmit control register (address 30) bit name description type 2 default 30.15:11 reserved ignore r/w 0 30.12 transmit low power 1 = forces the transmitter into low power mode. also forces a zero-differential transmission. 0 = normal transmission. r/w 0 30.11:10 port rise time control 1 00 = 3.0 ns (default = txslew<1:0> pins) 01 = 3.4 ns 10 = 3.9 ns 11 = 4.4 ns r/w 00 30.9:0 reserved ignore r/w 0 1. values are relative approximations. not guaranteed or production tested. 2. r/w = read/write
lxt971a 3.3v dual-speed fast ethernet transceiver 88 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 7.0 package specifications figure 43. pbga package specification 1.26 0.10 0.70 0.025 0.26 0.04 0.28 0.10 3 seating plane side view 2.00 ref. top view bottom view option: pin a1 identifier 1.00 0.10 ink or laser marking c a 7.00 0.20 b 7.00 0.20 2.00 ref. 0.20 (4x) notes: 1. all dimensions and tolerances conform to asme y 14.5 m - 1994. 2. dimension is measured at the maximum solder ball diameter, parallel to primary datum c. 3. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 4. maximum mold to substrate offset shall be 0.127. 5. the surface finish of the package shall be edm charmille #18 - #21. 6. unless otherwise specified tolerance: decimal 0.05 angular 2. b h g f e d c a 8765 432 1 2 0.70 ref. 6.30 0.80 0.40 0.15 0.30 0.15 c c b a 64-ball plastic ball grid array package ? part number - lxt971abc commercial temperature range (0oc to +70oc) ? part number - lxt971abe exte nded temperature range (-40oc to +85oc)
lxt971a 3.3v dual-speed fast ethernet transceiver datasheet 89 document #: 249414 revision #: 002 rev. date: august 7, 2002 figure 44. lxt971a lqfp package specifications d d 1 a 1 a 2 l a b l 1 3 3 e e 1 e / 2 e 64-pin low profile quad flat pack ? part number - lxt971alc commerci al temperature range (0oc to +70oc) ? part number - lxt971ale extend ed temperature range (-40oc to +85oc) dim millimeters min max a ? 1.60 a 1 0.05 0.15 a 2 1.35 1.45 b 0.17 0.27 d 11.85 12.15 d 1 9.9 10.1 e 11.85 12.15 e 1 9.9 10.1 e 0.50 bsc 1 l 0.45 0.75 l 1 1.00 ref 3 11 o 13 o 0 o 7 o 1. basic spacing between centers
lxt971a 3.3v dual-speed fast ethernet transceiver 90 datasheet document #: 249414 revision #: 002 rev. date: august 7, 2002 8.0 product ordering information table 59. product information number revision qualification tray mm tape & reel mm djlxt971alc.a4 a4 s 834105 834916 djlxt971ale.a4 a4 s 835676 835791 fllxt971abc.a4 a4 s 834103 834926 fllxt971abe.a4 a4 s 834104 835080 figure 45. ordering information - sample temperature range a c e = ambient (0 - 55 c) = commercial (0 - 70 c) = extended (-40 - +85 c) product revision xn = 2 alphanumeric characters build format e000 e001 = tray = tape and reel dj s a4 c l 971a lxt e001 internal package designator l p n q h t b c e k = lqfp = plcc = dip = pqfp = qfp with heat spreader = tqfp = bga = cbga = tbga = hsbga (bga with heat slug) qualification q s = pre-production material = production material ixa product prefix lxt ixe ixf ixp = phy layer device = switching engine = formatting device (mac) = network processor intel package designator dj fa fl fw hb hd hf hg s gc n = lqfp = tqfp = pbga (<1.0 mm pitch) = pbga (1.27 mm pitch) = qfp with heat spreader = qfp with heat slug = cbga = soic = qfp = tbga = plcc xxxx = 3-5 digit alphanumeric product code

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